公开(公告)号：US08321598B2

公开(公告)日：2012-11-27

申请号：US12112176

申请日：2008-04-30

申请人： James Boomer ,  Oscar Freitas

发明人： James Boomer ,  Oscar Freitas

IPC分类号： G06F3/00

CPC分类号： H03M11/20

摘要： A serializer/deserializer interfacing a keypad or keyboard to a processing system is illustrated. However, to minimize wires on intervening cables, a serializer and deserializer is inserted between the processor system and the keypad forming a virtual keypad. The processor scans the deserializer as if it were the keypad and the keypad is scanned by the serializer as if it were the processor. The serializer converts the scanning of the keypad into a serial bit stream and clock that is sent to the deserializer. The deserializer accepts the serial bit stream and reconfigures the data into a response that mimics the response of the physical keypad. In one embodiment an actual second keypad is formed in the deserializer and activated as the first keypad is activated.

摘要翻译： 示出了将键盘或键盘连接到处理系统的串行器/解串器。 然而，为了最小化插入电缆的电线，串行器和解串器插入在处理器系统和形成虚拟键盘的键盘之间。 处理器扫描解串器，就像它是键盘一样，键盘由串行器扫描，就像处理器一样。 串行器将键盘的扫描转换为串行位流和发送到解串器的时钟。 解串器接受串行位流，并将数据重新配置为模拟物理键盘响应的响应。 在一个实施例中，在解串器中形成实际的第二键盘，并且当第一键盘被激活时被激活。

公开(公告)号：US20050231399A1

公开(公告)日：2005-10-20

申请号：US10824747

申请日：2004-04-15

申请人： Michael Fowler ,  James Boomer

发明人： Michael Fowler ,  James Boomer

IPC分类号： H03M7/00 ,  H03M9/00 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033

CPC分类号： H03M9/00 ,  H04J3/0614 ,  H04L7/0091 ,  H04L7/033

摘要： A serializer and a deserializer are disclosed and shown operating singly or as a pair. The invention operates independently from any outside system reference clock. The inventive system provides an internal bit clock that serializes the data when sending and de-serializes the data when receiving. A bit clock or pulse travels with the data word bits to define when a bit is stable. The system uses word boundary bits operating with a bit clock to distinguish different data words, as described in the parent application. The system operates either synchronously or asynchronously with the base computer or other such digital system, including I/O devices. The invention finds use where new data to be sent is strobed into the serializer, but also where a change in the data bit content itself will cause the changed data to be loaded into the serializer and sent bit by bit. The system operates where new data is strobed or loaded by the serializer (not the base computer system) when the last data word has been sent. In this case a signal is generated when the last word has been sent in the serializer that causes new data to be loaded for sending. Half duplex and full duplex configurations as disclosed. Similar, corresponding operations occur at the deserializer.

摘要翻译： 串行器和解串器被公开并示出为单独操作或一对操作。 本发明独立于任何外部系统参考时钟工作。 本发明的系统提供内部位时钟，其在接收时发送和解串行化数据时串行化数据。 一个位时钟或脉冲随着数据字位移动，以定义位何时稳定。 系统使用以位时钟操作的字边界位来区分不同的数据字，如父应用程序所述。 该系统与基本计算机或其他此类数字系统（包括I / O设备）同步或异步运行。 本发明用于将要发送的新数据选通到串行器中，而且数据位内容本身的变化将导致改变的数据被加载到串行器中并逐位发送的地方。 当最后一个数据字被发送时，该系统在串行器（而不是基本计算机系统）选通或加载新数据的情况下运行。 在这种情况下，当序列化程序中发送最后一个单词时会产生一个信号，从而导致新的数据被加载发送。 所公开的半双工和全双工配置。 类似的，相应的操作发生在解串器。

公开(公告)号：US06433613B1

公开(公告)日：2002-08-13

申请号：US09737977

申请日：2000-12-15

申请人： Trenor Goodell ,  James Boomer

发明人： Trenor Goodell ,  James Boomer

IPC分类号： H03K17687

CPC分类号： H03K17/162 ,  H03K17/687

摘要： A translation switch is described with a transfer MOS transistor that connects a first node to second node where the first node is referenced to a higher voltage than is the second. A pseudo-rail generator drives the gate of the MOS transistor and provides a p-rail reference voltage lower in voltage to that of the first node. The generator includes a selectively enabled active clamping circuit that clamps the gate of the MOS transfer transistor to the p-rail potential and sinks current from the p-rail when higher voltages appear on the p-rail to thereby maintain the p-rail at a substantially constant potential.

摘要翻译： 使用传输MOS晶体管描述转换开关，该MOS晶体管将第一节点与第二节点相连，第二节点的第一节点被参考为比第二节点更高的电压。 伪轨发电机驱动MOS晶体管的栅极，并提供与第一节点相比电压更低的p-rail参考电压。 该发生器包括有选择地启用的有源钳位电路，其将MOS转移晶体管的栅极夹持到p轨电位，并在p型导轨上出现较高电压从而吸收来自p型导轨的电流，从而将p型导轨保持在 基本恒定的电位。

公开(公告)号：US714478A

公开(公告)日：1902-11-25

申请号：US1901067176

申请日：1901-07-05

申请人： HALL JAMES BOOMER

发明人： HALL JAMES BOOMER

CPC分类号： F24H1/06 ,  A61H33/063

公开(公告)号：US08170070B2

公开(公告)日：2012-05-01

申请号：US12112136

申请日：2008-04-30

申请人： James Boomer ,  Oscar Freitas

发明人： James Boomer ,  Oscar Freitas

IPC分类号： H04J3/02

CPC分类号： H04J3/047 ,  G09G5/006 ,  H04M1/0214 ,  H04M1/23 ,  H04M2250/52

摘要： A system for interleaving high speed data and slower data that is serialized and delivered to a microprocessor. The typical source of the high speed data is a camera and the source of the slower data is a keyboard. The high speed data and the slower data, illustratively, are interfaced with a micro-processor in a parallel fashion. The present invention mirrors the parallel interface to the microprocessor, and mirrors the parallel interface to the sources of the high speed (camera) and slower (keypad) data. The present system formats parallel data from the sources and passes that data in serial form, typically with a clock, on a flexible cable that joins two sections of many cell phones or other hand held devices.

摘要翻译： 用于交错高速数据和慢速数据的系统，其被串行化并传送到微处理器。 高速数据的典型来源是相机，较慢数据的来源是键盘。 示例性地，高速数据和较慢的数据以并行方式与微处理器接口。 本发明反映了与微处理器的并行接口，并且反映了与高速（摄像机）和较慢（小键盘）数据源的并行接口。 本系统将来自源的并行数据格式化，并将该数据以串行形式（通常为时钟）传送到连接许多手机或其他手持设备的两部分的柔性电缆上。

公开(公告)号：US20050219083A1

公开(公告)日：2005-10-06

申请号：US10802372

申请日：2004-03-16

申请人： James Boomer ,  Michael Fowler

发明人： James Boomer ,  Michael Fowler

IPC分类号： H03M9/00 ,  H04L7/00 ,  H04L7/04 ,  H04L7/06 ,  H04L25/49

CPC分类号： H04L7/0008 ,  H04L7/04 ,  H04L7/06 ,  H04L2007/045

摘要： A bi-directional serializer/deserializer is disclosed using a single bi-directional data line and a single bi-directional clock line. Gated buffers are controlled to operate either sending or receiving data, and a phase locked loop provides a clock to shift data out from a shift register. A reference clock is supplied to the PLL and the PLL generates a synchronous bit clock. The bit clock is sent over the clock line in parallel with the serial data bits, and the PLL bit clock is synchronized to the data bits. The receiving system will use the bit clock to serial load a receiving shift register. When a word is received a word clock is available to inform the receiving system. An embodiment of the system sends data to a receiving system using a clock generated at the sending system. Another embodiment receives data but uses a clock that is sent from the receiving system to the sending system, wherein the sending system uses the received clock to generate a clock to send the data and a synchronous clock that is sent back to the receiving system to load the data from the data line.

摘要翻译： 公开了使用单个双向数据线和单个双向时钟线的双向串行器/解串器。 门控缓冲器被控制以发送或接收数据，并且锁相环提供用于从移位寄存器移出数据的时钟。 参考时钟提供给PLL，PLL产生同步位时钟。 位时钟通过时钟线与串行数据位并行发送，PLL位时钟与数据位同步。 接收系统将使用位时钟来串行加载接收移位寄存器。 当接收到一个字时，可以使用一个字时钟通知接收系统。 系统的一个实施例使用在发送系统产生的时钟将数据发送到接收系统。 另一个实施例接收数据，但是使用从接收系统发送到发送系统的时钟，其中发送系统使用所接收的时钟来产生发送数据的时钟和发送回接收系统的同步时钟以加载 来自数据线的数据。

公开(公告)号：US20050207280A1

公开(公告)日：2005-09-22

申请号：US10802436

申请日：2004-03-16

申请人： Michael Fowler ,  James Boomer ,  Nathan Charland

发明人： Michael Fowler ,  James Boomer ,  Nathan Charland

IPC分类号： H03M9/00 ,  H04L5/14 ,  H04L7/00 ,  H04L7/04 ,  H04L7/06 ,  H04L25/45 ,  H04L25/49 ,  G04B47/00 ,  G06F11/00 ,  H03M13/00

CPC分类号： H04L7/0008 ,  H03M9/00 ,  H04L5/14 ,  H04L7/04 ,  H04L7/06 ,  H04L25/45 ,  H04L2007/045

摘要： A bi-directional serializer/deserializer is disclosed using a single bi-directional data line and a single bi-directional clock line. Gated buffers are controlled to operate either sending or receiving data, and a phase locked loop provides a clock to shift data out from a shift register. A reference clock is supplied to the PLL and the PLL generates a synchronous bit clock. The bit clock is sent over the clock line in parallel with the serial data bits, and the PLL bit clock is synchronized to the data bits. Two data boundary bits are inserted between the word data bits, the boundary data bits are arranged with a logic level transition between the two data boundary bits. Also, at the boundary of the words during the sending of the two boundary data bits, the synchronous bit clock is arranged to have no logic level transition. The receiving system will use the bit clock to serial load the received word and boundary data bits into a shift register. A word boundary is detected by sensing a data bit transition while there is no bit clock.

摘要翻译： 公开了使用单个双向数据线和单个双向时钟线的双向串行器/解串器。 门控缓冲器被控制以发送或接收数据，并且锁相环提供用于从移位寄存器移出数据的时钟。 参考时钟提供给PLL，PLL产生同步位时钟。 位时钟通过时钟线与串行数据位并行发送，PLL位时钟与数据位同步。 在字数据位之间插入两个数据边界位，边界数据位以两个数据边界位之间的逻辑电平转换排列。 而且，在发送两个边界数据位期间的字边界处，同步位时钟被布置成没有逻辑电平转换。 接收系统将使用位时钟将接收的字和边界数据位串行加载到移位寄存器中。 通过在没有位时钟的情况下感测数据位转换来检测字边界。

公开(公告)号：US20090110130A1

公开(公告)日：2009-04-30

申请号：US12112152

申请日：2008-04-30

申请人： James Boomer ,  Oscar Freitas ,  Steven Macaluso

发明人： James Boomer ,  Oscar Freitas ,  Steven Macaluso

IPC分类号： H04L7/00

CPC分类号： H04B3/30

摘要： A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.

摘要翻译： 用于消除彼此通信的逻辑系统之间的控制线的系统和过程。 在一个实施例中，系统向接收机发送指示第一模式的频率。 在第一模式中，可以发送第一数据类型。 当频率改变时，指示可以发送第二数据类型的第二模式。 接收机检测频率变化并采取所指示的第一或第二模式。

公开(公告)号：US20090106462A1

公开(公告)日：2009-04-23

申请号：US12112176

申请日：2008-04-30

申请人： James Boomer ,  Oscar Freitas

发明人： James Boomer ,  Oscar Freitas

IPC分类号： G06F3/02

CPC分类号： H03M11/20

摘要： A serializer/deserializer interfacing a keypad or keyboard to a processing system is illustrated. In one application, the processor is arranged to generate keypad scan and input keypad sense lines directly. However, to minimize wires on intervening cables, a serializer and deserializer is inserted between the processor system, the serializer/deserializer forming a virtual keypad. In this case, the processor scans the deserializer as if it were the keypad and the keypad is scanned by the serializer as if it were the processor. However, the serializer converts the scanning of the keypad into a serial bit stream that is sent to the deserializer using only a data line and a clock line. The deserializer accepts the serial bit stream and reconfigures the data into a response that mimics the response of the physical keypad as the computer system scans the virtual keypad, the deserializer. In one embodiment an actual second keypad is formed in the deserializer and activated as the first keypad is activated, wherein the computer scans the second keypad in the usual fashion.

摘要翻译： 示出了将键盘或键盘连接到处理系统的串行器/解串器。 在一个应用中，处理器被布置成直接产生键盘扫描和输入键盘感测线。 然而，为了最小化插入电缆的电线，串行器和解串器插入处理器系统之间，串行器/解串器形成虚拟键盘。 在这种情况下，处理器扫描解串器，就像它是键盘一样，键盘由串行器扫描，就像处理器一样。 然而，串行器将键盘的扫描转换成仅使用数据线和时钟线发送到解串器的串​​行比特流。 解串器接受串行位流，并将数据重新配置为当计算机系统扫描虚拟键盘（即串并行器）时模拟物理键盘的响应的响应。 在一个实施例中，在解串器中形成实际的第二键盘，并且当第一键盘被激活时被激活，其中计算机以通常的方式扫描第二键盘。

公开(公告)号：US08107575B2

公开(公告)日：2012-01-31

申请号：US12112152

申请日：2008-04-30

申请人： James Boomer ,  Oscar Freitas ,  Steven Macaluso

发明人： James Boomer ,  Oscar Freitas ,  Steven Macaluso

IPC分类号： H04L7/00

CPC分类号： H04B3/30

摘要： A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency is changed a second mode is indicated wherein a second data type may be sent. The receiver detects the frequency change and assumes the first or second mode as indicated.

摘要翻译： 用于消除彼此通信的逻辑系统之间的控制线的系统和过程。 在一个实施例中，系统向接收机发送指示第一模式的频率。 在第一模式中，可以发送第一数据类型。 当频率改变时，指示可以发送第二数据类型的第二模式。 接收机检测频率变化并采取所指示的第一或第二模式。