公开(公告)号：US5477068A

公开(公告)日：1995-12-19

申请号：US32119

申请日：1993-03-17

申请人： Takanori Ozawa

发明人： Takanori Ozawa

IPC分类号： G11C16/04 ,  H01L29/423 ,  H01L29/788

CPC分类号： G11C16/0433 ,  H01L29/42328 ,  H01L29/7885

摘要： A pair of impurity regions are formed at a specified interval in a semiconductor substrate. A channel region is defined between the impurity regions. A select gate is provided on the channel region, and a sidewall for holding electric charge is provided along a side of the select gate. A tunnel insulating film is interposed between the sidewall for holding electric charge and the channel region. An insulating film covers the sidewall for holding electric charge. A control gate is provided on the insulating film lying over the sidewall. In such a structure, since the select gate can have a large cross-sectional area, speed-up of the reading can be attained.

摘要翻译： 在半导体衬底中以指定的间隔形成一对杂质区。 在杂质区域之间限定沟道区域。 在通道区域设置选择栅极，沿着选择栅极侧设置用于保持电荷的侧壁。 隧道绝缘膜介于用于保持电荷的侧壁和沟道区之间。 绝缘膜覆盖侧壁以保持电荷。 在位于侧壁上的绝缘膜上设置控制栅极。 在这种结构中，由于选择栅极可以具有大的横截面积，所以可以实现读取的加速。

公开(公告)号：USD673480S1

公开(公告)日：2013-01-01

申请号：US29416760

申请日：2012-03-27

申请人： Keiichi Keyaki ,  Takanori Ozawa ,  Yuichi Iwase

设计人： Keiichi Keyaki ,  Takanori Ozawa ,  Yuichi Iwase

公开(公告)号：USD656433S1

公开(公告)日：2012-03-27

申请号：US29390828

申请日：2011-04-29

申请人： Takanori Ozawa

设计人： Takanori Ozawa

公开(公告)号：USD631790S1

公开(公告)日：2011-02-01

申请号：US29363902

申请日：2010-06-16

申请人： Keiichi Keyaki ,  Koji Yamagishi ,  Takanori Ozawa

设计人： Keiichi Keyaki ,  Koji Yamagishi ,  Takanori Ozawa

公开(公告)号：USD621297S1

公开(公告)日：2010-08-10

申请号：US29328886

申请日：2008-12-03

申请人： Miyuki Ohgaku ,  Takanori Ozawa

设计人： Miyuki Ohgaku ,  Takanori Ozawa

公开(公告)号：US06580634B2

公开(公告)日：2003-06-17

申请号：US09969211

申请日：2001-10-01

申请人： Takaaki Fuchikami ,  Takanori Ozawa

发明人： Takaaki Fuchikami ,  Takanori Ozawa

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A data memory device is provided that is capable of reading data accurately even if the reading action is repeated. Respective output ends of memory cells D0-D7 and input ends on one side of respective exclusive OR elements Eo0-Eo7 are interconnected, and the output end of a polarity holding cell Dc and the input ends on the other side of the respective exclusive OR elements Eo0-Eo7 are interconnected. When it is assumed that the stored value of the memory cell D0 is a logic “1” and the stored value of the polarity holding cell Dc is a logic “0,” the value of the output data Do0 read out becomes a logic “1”. By the reversal writing action that follows, the value of the memory cell D0 becomes a logic “0” and the stored value of the polarity holding cell Dc becomes a logic “1.” When the value of the memory cell D0 is read again in that state, the value of the output data Do0 is still a logic “1.” That is to say, even if data reading action is repeated, values of the output data Do0-Do7 remain unchanged. However, the direction of polarization of respective ferroelectric capacitors constituting the memory cells D0-D7 and the polarity holding cell Dc are reversed every time of the reading.

摘要翻译： 提供了即使重复读取动作也能够准确地读取数据的数据存储装置。 存储单元D0-D7的各个输出端和相应异或元件Eo0-Eo7的一侧上的输入端相互连接，极性保持单元Dc的输出端和输入端在各自的异或元件的另一侧 Eo0-Eo7是互连的。 当假设存储单元D0的存储值为逻辑“1”且极性保持单元Dc的存储值为逻辑“0”时，读出的输出数据Do0的值成为逻辑“1” “。 通过随后的反转写入动作，存储单元D0的值成为逻辑“0”，极性保持单元Dc的存储值变为逻辑“1”。 当在该状态下再次读出存储单元D0的值时，输出数据Do0的值仍为逻辑“1”。 也就是说，即使重复数据读取动作，输出数据Do0-Do7的值保持不变。 然而，构成存储单元D0-D7的各个强电介质电容器的极化方向和极性保持单元Dc在每次读取时都反转。

公开(公告)号：US06545901B2

公开(公告)日：2003-04-08

申请号：US09953091

申请日：2001-09-13

申请人： Takaaki Fuchikami ,  Takanori Ozawa

发明人： Takaaki Fuchikami ,  Takanori Ozawa

IPC分类号： G11C1122

CPC分类号： G11C11/22 ,  G11C7/062

摘要： A semiconductor memory device including a memory element for storing data, and a supplemental element substantially electrically associated with the memory element at least at the time of reading data. The semiconductor memory device is for reading data stored in the memory element by applying specified electric action to the compound element including the memory element and the supplemental element substantially electrically mutually associated. The semiconductor memory device is characterized in that the electric characteristic of the supplemental element is adapted to be variable based on a signal for changing the electric characteristic of the supplemental element so that data may be read free from troubles.

摘要翻译： 至少在读取数据时，包括用于存储数据的存储元件的半导体存储器件和与存储器元件基本电气相关的补充元件。 半导体存储器件用于通过对包括存储元件和补充元件的复合元件基本上电相互关联的特定电作用来读取存储在存储元件中的数据。 半导体存储器件的特征在于，补充元件的电特性基于用于改变补充元件的电特性的信号而变化，从而可以读出数据不受麻烦。

公开(公告)号：US06535421B1

公开(公告)日：2003-03-18

申请号：US09500385

申请日：2000-02-08

申请人： Takanori Ozawa

发明人： Takanori Ozawa

IPC分类号： G11C2900

CPC分类号： G11C29/12005 ,  G11C5/14 ,  G11C5/147 ,  G11C11/22 ,  G11C16/04 ,  G11C29/12 ,  G11C2029/1202

摘要： A nonvolatile semiconductor memory which includes a voltage supply terminal, a multiplicity of memory cells, a voltage selection circuit, and a voltage dropping circuit. The terminal receives a supply voltage from an external voltage source. The voltage selection circuit is coupled to the terminal for selectively outputting a first and a second voltage to be supplied to the memory cells. The voltage dropping circuit is coupled between the voltage selection circuit and the memory cells for dropping the second voltage output from the voltage selection circuit before it is input to the memory cells.

摘要翻译： 一种非易失性半导体存储器，包括电压源端子，多个存储单元，电压选择电路和降压电路。 终端从外部电压源接收电源电压。 电压选择电路耦合到端子，用于选择性地输出要提供给存储单元的第一和第二电压。 电压下降电路耦合在电压选择电路和存储单元之间，用于在电压选择电路被输入到存储单元之前将其从电压选择电路输出的次数下降。

公开(公告)号：US5563081A

公开(公告)日：1996-10-08

申请号：US561324

申请日：1995-11-21

申请人： Takanori Ozawa

发明人： Takanori Ozawa

IPC分类号： G11C11/22 ,  H01L27/115 ,  H01L21/8239

CPC分类号： H01L27/11502 ,  G11C11/22 ,  Y10S148/139 ,  Y10S148/14

摘要： A method for making a nonvolatile memory device having a field effect transistor for storing information, and a Schottky diode in series with the field effect transistor. The field effect transistor includes source and drain regions in a semiconductor substrate, with a channel region interposed between them and a gate electrode above the channel region. A ferroelectric gate film is sandwiched between the channel region and the gate electrode. In the method, a conductive barrier meterial is deposited in contact with the source region of the field effect transistor to make the Schottky diode. In reading information from the memory device, voltage is applied to a serial circuit consisting of the field effect transistor and the Schottky diode to turn the Schottky diode on.

摘要翻译： 一种用于制造具有用于存储信息的场效应晶体管的非易失性存储器件的方法和与场效应晶体管串联的肖特基二极管。 场效应晶体管包括半导体衬底中的源极和漏极区域，沟道区域介于它们之间，栅极电极位于沟道区域上方。 铁电栅极膜夹在沟道区和栅电极之间。 在该方法中，导电阻挡层被沉积成与场效应晶体管的源极区接触以制成肖特基二极管。 在从存储器件读取信息时，将电压施加到由场效应晶体管和肖特基二极管组成的串联电路以使肖特基二极管导通。

公开(公告)号：US5498888A

公开(公告)日：1996-03-12

申请号：US212719

申请日：1994-03-14

申请人： Takanori Ozawa

发明人： Takanori Ozawa

IPC分类号： H01L27/10 ,  G06N3/063 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/7881 ,  G06N3/0635

摘要： A semiconductor device having a source region, a drain region, a channel region between the source region and the drain region, a gate consisting of at least three input electrodes provided above the channel region, and a potential modulating film provided between the channel region and the gate. The potential modulating film can assume at least two potential modulating states, so that the potential of the channel region is modulated between and held at different values. The potential of the channel region is modulated by changing the state of the potential modulating film. Specifically, the potential of the channel region is modulated by not only applying voltages to the input electrodes but also controlling the state of the potential modulating film. If in processing at least three input signals, a predetermined one of them corresponds to control of the state of the potential modulating film and the remaining input signals correspond to the input voltages to the input electrodes, the number of wires can be decreased.

摘要翻译： 一种半导体器件，具有源极区域，漏极区域，源极区域和漏极区域之间的沟道区域，由至少三个设置在沟道区域上方的输入电极组成的栅极以及设置在沟道区域和沟道区域之间的电位调制膜 大门。 电位调制膜可呈现至少两个电势调制状态，使得沟道区的电位在不同的值之间调制并保持在不同的值。 通过改变电位调制膜的状态来调制沟道区的电位。 具体地，通过不仅对输入电极施加电压而且控制电位调节膜的状态来调制沟道区域的电位。 如果在处理至少三个输入信号时，其预定的一个对应于电位调制膜的状态的控制，其余的输入信号对应于输入电极的输入电压，则可以减少导线的数量。