公开(公告)号：US5610097A

公开(公告)日：1997-03-11

申请号：US615106

申请日：1996-03-14

Applicant: Takashi Shimizu

Inventor： Takashi Shimizu

IPC: C23C14/24 ,  H01L21/203 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/47 ,  H01L29/872 ,  H01L21/44

CPC classification number: H01L21/32051 ,  Y10S148/139 ,  Y10S148/14

Abstract: A method for forming electrodes on a semiconductor includes introducing at least one reactive oxidizing gas selected from the group consisting of ozone, atomic oxygen, nitrogen dioxide, oxygen ion and oxygen plasma to an oxide semiconductor surface and depositing electrode material on the oxide semiconductor surface without exposing the surface to the outside atmosphere.

Abstract translation: 在半导体上形成电极的方法包括将选自臭氧，原子氧，二氧化氮，氧离子和氧等离子体的至少一种反应性氧化气体引入到氧化物半导体表面，并且在氧化物半导体表面上沉积电极材料而没有 将表面暴露于外部气氛。

公开(公告)号：US5358885A

公开(公告)日：1994-10-25

申请号：US46811

申请日：1993-04-16

Applicant: Tomoki Oku ,  Masayuki Sakai ,  Yasutaka Kohno

Inventor： Tomoki Oku ,  Masayuki Sakai ,  Yasutaka Kohno

IPC: H01L21/285 ,  H01L21/335 ,  H01L29/423 ,  H01L21/44

CPC classification number: H01L29/66462 ,  H01L21/28587 ,  H01L29/42316 ,  Y10S148/10 ,  Y10S148/139 ,  Y10S438/951

Abstract: A method of producing a field effect transistor includes depositing a first insulating film and a refractory metal on a semiconductor substrate, forming a first aperture penetrating the first insulating film and the refractory metal film to provide a gate electrode production region, depositing a second insulating film on the refractory metal film, etching the second insulating film in a direction perpendicular to the surface of the substrate leaving portions of the second insulating film on opposite side walls of the first aperture to form a second aperture, defining a gate length, depositing a gate metal, and patterning the gate metal layer, the first insulating film, and the refractory metal film in a prescribed width to form a T-shaped gate structure. During etching the second insulating film, since the refractory metal film serves as a etch stopping layer, the first insulating film is not etched and its thickness remains as deposited. Therefore, the space between the over-hanging portion of the T-shaped gate electrode and the source electrode increases and the gate-to-source capacitance is reduced.

Abstract translation: 制造场效应晶体管的方法包括在半导体衬底上沉积第一绝缘膜和难熔金属，形成穿透第一绝缘膜的第一孔和难熔金属膜以提供栅电极生产区，沉积第二绝缘膜 在所述难熔金属膜上，在垂直于所述基板的表面的方向上蚀刻所述第二绝缘膜，从而将所述第二绝缘膜的部分留在所述第一孔的相对侧壁上，以形成限定栅极长度的第二孔， 金属，并以规定的宽度图案化栅极金属层，第一绝缘膜和难熔金属膜，以形成T形栅极结构。 在蚀刻第二绝缘膜期间，由于难熔金属膜用作蚀刻停止层，所以第一绝缘膜不被蚀刻并且其厚度保持沉积。 因此，T形栅电极的过悬挂部分与源电极之间的空间增加，并且栅极 - 源极电容减小。

公开(公告)号：US5268316A

公开(公告)日：1993-12-07

申请号：US898136

申请日：1992-06-12

Applicant: Murray J. Robinson ,  Christopher C. Joyce ,  Tim Wah Luk

Inventor： Murray J. Robinson ,  Christopher C. Joyce ,  Tim Wah Luk

IPC: H01L27/06 ,  H01L21/265

CPC classification number: H01L27/0623 ,  H01L27/0664 ,  Y10S148/139 ,  Y10S148/14

Abstract: An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction. The improved Schottky diode structure may be formed as part of a BICMOS integrated circuit fabrication process wherein the buried diode layer may be formed at the same time as a buried collector layer of a bipolar transistor structure, the diode NWell may be formed at the same time as an NWell of a CMOS transistor structure and the diode ohmic contact region may be formed at the same time as a collector sink region. In the BICMOS fabrication process the buried collector layer definition mask is also a buried diode layer definition mask, the retro NWell definition mask is also a diode NWell definition mask, the collector sink definition mask is also a diode ohmic contact region definition mask, and the BICMOS contacts definition mask is also a diode junction and ohmic contact definition mask.

Abstract translation: 改进的肖特基二极管结构（4）通过逆向扩散相对较快的扩散原子（优选磷原子）的N +浓度形成，以形成二极管的二极管衬底的局部二极管NWell（6）。 由较慢扩散的N型原子（优选为锑原子）形成的埋二极管层（5）位于二极管NWell的下面，并将二极管结（7）电耦合到二极管欧姆接触（9）。 二极管欧姆接触区（31）位于欧姆接触之下，进一步将二极管结耦合到欧姆接触。 优选地，二极管结是铂 - 硅化物结。 改进的肖特基二极管结构可以形成为BICMOS集成电路制造工艺的一部分，其中埋入二极管层可以与双极晶体管结构的掩埋集电极层同时形成，二极管NWell可以同时形成 作为CMOS晶体管结构的栅极，并且二极管欧姆接触区域可以与集电极阱区域同时形成。 在BICMOS制造工艺中，掩埋集电极层定义掩模也是埋地二极管层定义掩模，复古NWell定义掩模也是二极管NWell定义掩模，集电极阱定义掩模也是二极管欧姆接触区域定义掩模，而 BICMOS触点定义掩模也是二极管结和欧姆接触定义掩模。

公开(公告)号：US4769338A

公开(公告)日：1988-09-06

申请号：US23344

申请日：1987-03-09

Applicant: Stanford R. Ovshinsky ,  Stephen J. Hudgens

Inventor： Stanford R. Ovshinsky ,  Stephen J. Hudgens

IPC: H01L21/324 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/04 ,  H01L29/161 ,  H01L29/78 ,  H01L29/786 ,  H01L27/04 ,  H01L29/54

CPC classification number: H01L27/1214 ,  H01L21/324 ,  H01L29/04 ,  H01L29/161 ,  H01L29/66742 ,  H01L29/7839 ,  H01L29/78618 ,  H01L29/7866 ,  Y10S148/003 ,  Y10S148/122 ,  Y10S148/139 ,  Y10S148/15 ,  Y10S148/169

Abstract: There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprise rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.

Abstract translation: 公开了一种可以以快速切换速率操作的电影场效应晶体管，例如用于视频显示应用中。 晶体管包括具有比无定形材料更有序的结构的硅半导体材料体，并且比单晶材料有序。 晶体管的源极和漏极包括形成在硅半导体材料体上的整流触点。 还公开了制造晶体管和利用该晶体管的电子可寻址阵列系统的方法。

公开(公告)号：US4638551A

公开(公告)日：1987-01-27

申请号：US703703

申请日：1985-02-21

Applicant: Willem G. Einthoven

Inventor： Willem G. Einthoven

IPC: H01L29/06 ,  H01L29/872 ,  H01L29/48

CPC classification number: H01L29/872 ,  H01L29/0619 ,  Y10S148/042 ,  Y10S148/139 ,  Y10S148/14 ,  Y10S438/965

Abstract: An improved Schottky barrier device and method of manufacture is disclosed. The device has a semiconductor layer of first conductivity type; an insulating layer covering one face of the semiconductor layer, and has an opening therein. A conductor layer covers the semiconductor layer where the semiconductor layer is exposed by the opening and there forms a recitifying junction with the semiconductor layer. A first region of opposite conductivity type is at the one face of semiconductor layer and extends from where the conductor layer meets the insulating layer and below the conductor layer. A second region of opposite conductivity type is at the one face of semiconductor layer and begins where the conductor layer meets the insulating layer and extending below the insulating layer.

Abstract translation: 公开了一种改进的肖特基势垒器件及其制造方法。 该器件具有第一导电类型的半导体层; 覆盖半导体层的一个面的绝缘层，并且在其中具有开口。 导体层覆盖半导体层，其中半导体层被开口暴露，并且与半导体层形成再结合结。 相反导电型的第一区域位于半导体层的一个面上，并从导体层与绝缘层相遇并在导体层下方延伸。 相反导电类型的第二区域位于半导体层的一个表面，并且开始于导体层与绝缘层相交并延伸到绝缘层下方。

公开(公告)号：US4313971A

公开(公告)日：1982-02-02

申请号：US42920

申请日：1979-05-29

Applicant: Carl F. Wheatley, Jr.

Inventor： Carl F. Wheatley, Jr.

IPC: H01L21/285 ,  H01L21/225 ,  H01L29/48

CPC classification number: H01L21/28581 ,  H01L21/28537 ,  Y10S148/117 ,  Y10S148/139

Abstract: A Schottky barrier contact is formed by depositing the conductor portion of the Schottky barrier contact on a surface of a semiconductor from which a conductivity determining dopant has been leached to create a surface region of reduced dopant concentration. This process is compatible with the formation of an ohmic contact to an increased conductivity portion of the semiconductor material, an unleached portion of the semiconductor material or to a leached portion of the semiconductor material.

Abstract translation: 肖特基势垒接触是通过将肖特基势垒接触的导体部分沉积在半导体的表面上而形成的，该半导体的表面具有导电性确定掺杂剂已被浸出以形成掺杂浓度降低的表面区域。 该过程与形成与半导体材料的增加的导电部分，半导体材料的未漂白部分或半导体材料的浸出部分的欧姆接触相容。

公开(公告)号：US4222164A

公开(公告)日：1980-09-16

申请号：US974592

申请日：1978-12-29

Applicant: Sol Triebwasser

Inventor： Sol Triebwasser

IPC: H01L29/80 ,  H01L21/033 ,  H01L21/338 ,  H01L29/417 ,  H01L29/812 ,  B01J17/00

CPC classification number: H01L29/66848 ,  H01L21/033 ,  H01L29/812 ,  Y10S148/139 ,  Y10S148/141 ,  Y10S148/143

Abstract: A method for the production of metal-semiconductor field effect transistors (MESFET) is described. Practice of the method allows one to produce self-aligning MESFETs with Si sources and drains in close proximity having metal gates therebetween.

Abstract translation: 描述了用于制造金属 - 半导体场效应晶体管（MESFET）的方法。 该方法的实践允许产生具有Si源的自对准MESFET，并且在其间具有金属栅极紧邻的漏极。

公开(公告)号：US3961351A

公开(公告)日：1976-06-01

申请号：US521893

申请日：1974-11-07

Applicant: Victor Blatt

Inventor： Victor Blatt

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/48 ,  H01L29/56

CPC classification number: H01L27/0237 ,  H01L27/0688 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/087 ,  Y10S148/139

Abstract: An integrated circuit arrangement having at least one pair of superposed transistor structures which provides very high packing density and low power consumption. The arrangement includes first, second and third superposed semiconductive layers, the second layer being interposed between, and of the opposite conductivity type to, the first and third layers, and having a doping density higher than the first layer but lower than the third layer. At least one electrical contact is formed on a surface of the first layer and a plurality of spaced-apart semiconductive regions of the same conductivity type as the second layer are formed in the said surface of the first layer. An electrical contact is provided for each of the semiconductive regions and a layer of an electrical contact material is formed on a surface of the third layer. The doping density of the first layer can be such that the said at least one electrical contact forms a Schottky diode with the first layer.

Abstract translation: 一种具有至少一对重叠晶体管结构的集成电路装置，其提供非常高的封装密度和低功耗。 该布置包括第一，第二和第三叠置的半导体层，第二层介于第一和第三层之间且与第一和第三层之间具有相反的导电类型，并且具有高于第一层但低于第三层的掺杂密度。 在第一层的表面上形成至少一个电接触，并且在第一层的所述表面中形成与第二层相同的导电类型的多个间隔开的半导体区域。 为每个半导体区域提供电接触，​​并且在第三层的表面上形成电接触材料层。 第一层的掺杂密度可以使得所述至少一个电接触与第一层形成肖特基二极管。

公开(公告)号：US3953866A

公开(公告)日：1976-04-27

申请号：US468938

申请日：1974-05-10

Applicant: Lewis K. Russell

Inventor： Lewis K. Russell

IPC: G11C11/39 ,  G11C11/411 ,  H01L21/8229 ,  H01L27/07 ,  H01L27/082 ,  H01L27/102 ,  H03K3/289 ,  H01L27/02 ,  H01L27/04 ,  H03K3/26 ,  H03K5/00

CPC classification number: H03K3/289 ,  G11C11/39 ,  G11C11/4113 ,  H01L21/8229 ,  H01L27/0766 ,  H01L27/0828 ,  H01L27/1025 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/122 ,  Y10S148/139

Abstract: A semiconductor memory cell, and a method for fabrication, including a one conductivity semiconductor body having a major surface and an opposite conductivity layer formed on said major surface said layer having a planar surface. Means extend from said planar surface through said layer to contact said body for isolating portions of said layer into first and second device regions. First and second device regions each include a one conductivity region formed in said device region extending to said planar surface, an opposite conductivity region formed within said one conductivity regions extending to said surface, and a metal-to-semiconductor contact carried by said device region at said planar surface. Lead means include means for ohmic interconnection of opposite conductivity regions formed in said first and second device regions, means for interconnecting said first device region and said one conductivity region formed in said second device region. Lead means further includes means for interconnection of said second device region and said one conductivity region formed in said first device region. Additional lead means is provided for coupling said metal-to-semiconductor contacts, said semiconductor body and said interconnected opposite conductivity regions with external circuitry.

Abstract translation: 一种半导体存储单元及其制造方法，包括一个具有主表面和相反导电层的导电半导体本体，所述主导表面和相对的导电层形成在所述主表面上，所述层具有平坦表面。 装置从所述平面延伸穿过所述层以接触所述主体，用于将所述层的部分隔离成第一和第二装置区域。 第一和第二器件区域各自包括形成在延伸到所述平坦表面的所述器件区域中的一个导电区域，形成在延伸到所述表面的所述一个导电区域内的相反导电区域以及由所述器件区域承载的金属与半导体接触 在所述平面上。 引线装置包括用于在所述第一和第二器件区域中形成的相反导电区域的欧姆互连的装置，用于互连所述第一器件区域和形成在所述第二器件区域中的所述一个导电区域的装置。 引线装置还包括用于互连所述第二器件区域和形成在所述第一器件区域中的所述一个导电区域的装置。 提供附加的引线装置，用于将所述金属 - 半导体触点，所述半导体主体和所述互连的相对导电区域与外部电路耦合。

公开(公告)号：US3909807A

公开(公告)日：1975-09-30

申请号：US50267574

申请日：1974-09-03

Applicant: BELL TELEPHONE LABOR INC

Inventor： FULTON ALAN WILLIAM

IPC: G11C11/411 ,  H01L21/331 ,  H01L21/8229 ,  H01L27/00 ,  H01L27/102 ,  H01L29/73 ,  H03K3/286 ,  G11C11/40

CPC classification number: H03K3/286 ,  G11C11/4113 ,  H01L27/00 ,  H01L27/1025 ,  Y10S148/02 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/096 ,  Y10S148/109 ,  Y10S148/117 ,  Y10S148/139

Abstract: A cell for an integrated circuit memory is formed of two interconnected identical halves. Each such half is integrally formed without surface metal interconnections. The memory is fabricated from a semiconductor body which comprises an epitaxial layer of one conductivity type overlying a semiconductor substrate of the opposite type. Each half comprises a vertical npn transistor having the collector thereof at the exposed surface of the epitaxial layer and a lateral current source transistor. The collector region of each vertical transistor has two metal contacts, one to form a Schottky diode to couple to a bit line, and one to form an ohmic connection for crosscoupling of the two halves. Power is distributed by a line diffused in the epitaxial layer which line comprises the emitters of the lateral current source transistors and power is returned through word lines which are formed in the substrate of the body prior to growth of the epitaxial layer.

Abstract translation: 用于集成电路存储器的单元由两个互连的相同的一半形成。 每个这样的一半是整体形成的，没有表面金属互连。 存储器由半导体本体制成，该半导体主体包括覆盖相反类型的半导体衬底的一种导电类型的外延层。 每一半包括在外延层的暴露表面具有集电极的垂直npn晶体管和横向电流源晶体管。 每个垂直晶体管的集电极区域具有两个金属触点，一个形成肖特基二极管以耦合到位线，另一个用于形成用于两个半部的交叉耦合的欧姆连接。 功率通过扩散在外延层中的线分布，该线包括横向电流源晶体管的发射极，并且在外延层生长之前通过形成在体的衬底中的字线返回功率。