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公开(公告)号：US20050125585A1
公开(公告)日：2005-06-09
申请号：US11032051
申请日：2005-01-11
Applicant: Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
Inventor： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
CPC classification number: G06F13/4022 , G06F13/4027
Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
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公开(公告)号：US06810461B2
公开(公告)日：2004-10-26
申请号：US09983373
申请日：2001-10-24
Applicant: Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
Inventor： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC: G06F1314
CPC classification number: G06F13/4022 , G06F13/4027
Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
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公开(公告)号：US06219738B1
公开(公告)日：2001-04-17
申请号：US09514351
申请日：2000-02-28
Applicant: Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
Inventor： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
IPC: G06F1300
CPC classification number: G06F13/4027 , G06F13/36
Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
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公开(公告)号：US6128688A
公开(公告)日：2000-10-03
申请号：US296660
申请日：1999-04-23
Applicant: Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
Inventor： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
CPC classification number: G06F13/4027 , G06F13/36
Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
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公开(公告)号：US6078944A
公开(公告)日：2000-06-20
申请号：US831303
申请日：1997-04-01
Applicant: Yutaka Enko , Toshiaki Arai , Reki Yamamoto , Naofumi Shouji , Tomoki Sekiguchi , Tsutomu Noda , Tsuyoshi Watanabe , Tetsuya Mochida
Inventor： Yutaka Enko , Toshiaki Arai , Reki Yamamoto , Naofumi Shouji , Tomoki Sekiguchi , Tsutomu Noda , Tsuyoshi Watanabe , Tetsuya Mochida
IPC: G06F15/16 , G06F9/46 , G06F9/50 , G06F15/177 , G06F9/00
CPC classification number: G06F9/5088
Abstract: The parallelism of execution of processes in a memory shared multi-processor is enhanced. Each of a plurality of processors is provided with a run queue for holding executable processes, and a watch process for each processor to watch the execution status of its own to notify the rebuilding of the run queue to other processor and a rebuild step for rebuilding the run queue in response to the notice are stored in a shared memory as a program.
Abstract translation: 增强了存储器共享多处理器中进程的并行性。 多个处理器中的每一个都具有用于保持可执行过程的运行队列，以及用于每个处理器监视其自己的执行状态的监视处理，以将运行队列重建通知给其他处理器，以及重建步骤，用于重建 响应通知的运行队列作为程序存储在共享内存中。
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Patent Agency Ranking16.发明授权Bus control system incorporating the coupling of two split-transaction busses of different hierarchy 有权总线控制系统结合了不同层次结构的两个分组交易总线的耦合
公开(公告)号：US5941973A
公开(公告)日：1999-08-24
申请号：US203621
申请日：1998-12-01
Applicant: Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
Inventor： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
CPC classification number: G06F13/4027 , G06F13/36
Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
Abstract translation: 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块将发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。
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公开(公告)号：US07802045B2
公开(公告)日：2010-09-21
申请号：US12501684
申请日：2009-07-13
Applicant: Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
Inventor： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC: G06F13/00
CPC classification number: G06F13/4022 , G06F13/4027
Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
Abstract translation: 与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。 控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。 控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。
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公开(公告)号：US07577781B2
公开(公告)日：2009-08-18
申请号：US12155047
申请日：2008-05-29
Applicant: Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
Inventor： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC: G06F13/00
CPC classification number: G06F13/4022 , G06F13/4027
Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
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公开(公告)号：US07398346B2
公开(公告)日：2008-07-08
申请号：US11543878
申请日：2006-10-06
Applicant: Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
Inventor： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC: G06F13/00
CPC classification number: G06F13/4022 , G06F13/4027
Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
Abstract translation: 与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。 控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。 控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。
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公开(公告)号：US07177970B2
公开(公告)日：2007-02-13
申请号：US10274881
申请日：2002-10-22
Applicant: Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
Inventor： Nobukazu Kondo , Seiji Kaneko , Koichi Okazawa , Hideaki Gemma , Tetsuya Mochida , Takehisa Hayashi
CPC classification number: G06F13/4027 , G06F13/36
Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
Abstract translation: 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。
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