公开(公告)号：US20130314390A1

公开(公告)日：2013-11-28

申请号：US13983411

申请日：2012-07-25

申请人： Kaoru Yamamoto ,  Seiji Kaneko ,  Yasuyuki Ogawa ,  Kohhei Tanaka ,  Seiichi Uchida ,  Yutaka Takamaru ,  Shigeyasu Mori

发明人： Kaoru Yamamoto ,  Seiji Kaneko ,  Yasuyuki Ogawa ,  Kohhei Tanaka ,  Seiichi Uchida ,  Yutaka Takamaru ,  Shigeyasu Mori

IPC分类号： G09G3/36

CPC分类号： G09G3/36 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2310/0213 ,  G09G2310/0218 ,  G09G2310/0297 ,  G09G2320/0219 ,  G09G2330/023

摘要： There is provided an SSD display device with reduced power consumption.A selection circuit (400) consists of k selection blocks (410(1) to 410(k)). Each selection block consists of three thin-film. transistors. The three thin-film transistors respectively have three phases of selection control signal (CT) provided to their gate terminals. A scanning period (T1) is provided and followed by an idle period (T2). In the idle period (T2), the three thin-film transistors in each selection block are brought into ON state in accordance with selection control signals (CT) at an idle period frequency (fck2). The idle period frequency (fck2) is lower than a scanning period frequency (fck1).

摘要翻译： 提供了具有降低的功耗的SSD显示设备。 选择电路（400）由k个选择块（410（1）至410（k））组成。 每个选择块由三个薄膜组成。 晶体管。 三个薄膜晶体管分别具有提供给它们的栅极端子的选择控制信号（CT）的三相。 提供扫描期间（T1），并且后跟空闲期间（T2）。 在空闲时段（T2）中，根据空闲周期频率（fck2）的选择控制信号（CT），使每个选择块中的三个薄膜晶体管成为导通状态。 空闲周期频率（fck2）低于扫描周期频率（fck1）。

公开(公告)号：US20120146028A1

公开(公告)日：2012-06-14

申请号：US13391211

申请日：2010-07-26

申请人： Akihiro Oda ,  Seiji Kaneko

发明人： Akihiro Oda ,  Seiji Kaneko

IPC分类号： H01L29/786

CPC分类号： H01L27/1214 ,  H01L27/14601 ,  H01L31/02164 ,  H01L31/101

摘要： The light use efficiency of a thin film diode is improved even when the semiconductor layer of the diode has a small thickness, thereby improving the light detection sensitivity of the diode. Further, a short circuit between the electrodes of the thin film diode via the light-blocking layer is prevented. A thin film diode (130) having a first semiconductor layer (131) including, at least, an n-type region (131n) and a p-type region (131p) is provided on one side of a substrate (101), and a light-blocking layer (160) is provided between the substrate and the first semiconductor layer. A metal oxide layer (180) is provided on the side of the light-blocking layer facing the first semiconductor layer. Asperities are provided on the side of the metal oxide layer facing the first semiconductor layer, and the first semiconductor layer has a geometry of asperities conforming with the asperities on the metal oxide layer.

摘要翻译： 即使当二极管的半导体层具有小的厚度时，薄膜二极管的光利用效率也得到改善，从而提高二极管的光检测灵敏度。 此外，防止薄膜二极管经过遮光层的电极之间的短路。 具有至少包括n型区域（131n）和p型区域（131p）的第一半导体层（131）的薄膜二极管（130）设置在基板（101）的一侧，并且 在衬底和第一半导体层之间设置遮光层（160）。 金属氧化物层（180）设置在面向第一半导体层的遮光层的一侧。 在与第一半导体层相对的金属氧化物层的一侧设置有粗糙度，第一半导体层具有与金属氧化物层上的粗糙度一致的凹凸的几何形状。

公开(公告)号：US07380058B2

公开(公告)日：2008-05-27

申请号：US10666709

申请日：2003-09-19

申请人： Hiroki Kanai ,  Seiji Kaneko

发明人： Hiroki Kanai ,  Seiji Kaneko

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F1/26

CPC分类号： G06F11/2097 ,  G06F11/2089 ,  G06F12/0866 ,  G06F2212/312

摘要： A storage control apparatus comprising a plurality of channel control units each having an interface with an information processor; a disk control unit having an interface with a storage device for storing data; a cache memory for storing temporarily data to be interchanged between the information processor and the storage device; and an internal connector unit for connecting mutually the plurality of channel control units and the disk control unit, wherein the cache memory is disposed in each of the plurality of channel control units that are connected to one another through a dedicated data transfer path used for storing mutually the data stored in the cache memories.

摘要翻译： 一种存储控制装置，包括多个信道控制单元，每个信道控制单元具有与信息处理器的接口; 具有与用于存储数据的存储装置的接口的盘控制单元; 用于临时存储要在信息处理器和存储装置之间互换的数据的高速缓冲存储器; 以及用于连接多个通道控制单元和盘控制单元的内部连接器单元，其中，高速缓冲存储器设置在通过用于存储的专用数据传送路径彼此连接的多个通道控制单元中的每一个中 相互存储在缓存中的数据。

公开(公告)号：US07346754B2

公开(公告)日：2008-03-18

申请号：US11809110

申请日：2007-05-30

申请人： Seiji Kaneko

发明人： Seiji Kaneko

IPC分类号： G06F12/00

CPC分类号： G06F3/0661 ,  G06F3/0607 ,  G06F3/0689

摘要： Control methods are provided for a storage device controller system including first and second storage device controllers. Each of the first and second storage device controllers includes an I/O control module for communicating with a respective storage device storing data in a Fixed Block Architecture recording format, and a respective communications control module for receiving data requests for a respective storage device. The first storage device controller transmits a command to the second storage device controller if a data read request is received for data stored on storage device for the second storage device controller, and subsequently transmits the data that are read out from the storage device by the second storage device controller.

摘要翻译： 为包括第一和第二存储设备控制器的存储设备控制器系统提供控制方法。 第一和第二存储装置控制器中的每一个包括用于与以固定块结构记录格式存储数据的相应存储装置进行通信的I / O控制模块，以及用于接收对相应存储装置的数据请求的相应通信控制模块。 如果接收到用于第二存储设备控制器的存储设备上存储的数据的数据读取请求，则第一存储设备控制器向第二存储设备控制器发送命令，并且随后将从存储设备读出的数据发送到第二存储设备控制器 存储设备控制器

公开(公告)号：US20070106832A1

公开(公告)日：2007-05-10

申请号：US11642511

申请日：2006-12-21

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

公开(公告)号：US20070033342A1

公开(公告)日：2007-02-08

申请号：US11545514

申请日：2006-10-11

申请人： Seiji Kaneko ,  Hiroki Kanai

发明人： Seiji Kaneko ,  Hiroki Kanai

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0866 ,  G06F3/0611 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0689 ,  G06F12/0815 ,  G06F12/0817 ,  Y10S707/99952

摘要： A disk array device is equipped with a plurality of input/output channels that receive data input/output requests from an external device, a plurality of cache memories provided for the corresponding respective input/output channels, each of the cache memories connected to each of the corresponding respective input/output channels, a disk drive device, a disk control module that performs data input/output to and from the disk drive device, and a communication module that communicatively connects the input/output channels with the disk control module. The disk array device also includes a consistency maintaining module that can perform a consistency maintaining processing to maintain consistency of data stored in each of the cache memories. According to the content of the data input/output request received from the external device, an execution order of a response processing to respond to the external device according to the data input/output request and the consistency maintaining processing is controlled.

公开(公告)号：US20060168362A1

公开(公告)日：2006-07-27

申请号：US11386237

申请日：2006-03-21

申请人： Seiji Kaneko

发明人： Seiji Kaneko

IPC分类号： G06F3/00

CPC分类号： G06F3/0661 ,  G06F3/0607 ,  G06F3/0689

摘要： The present invention provides a control method for a storage device controller system provided with a first storage device controller that is connected to first and second storage devices storing data in the CKD format and the FBA format, respectively, and that has first and second communications control means that receive data input/output requests from a mainframe computer and an open system computer, respectively, and a second storage device that is connected to a third storage device storing data in the CKD format and that has third communications means connected to the second communications means, wherein the first storage device controller transmits a command to the second storage device controller if a data read request received from the open system computer is for data stored on the third storage device, and transmits the data that are read out from the third storage device by the second storage device controller to the open system computer.

摘要翻译： 本发明提供了一种具有第一存储装置控制器的存储装置控制系统的控制方法，所述第一存储装置控制器分别连接到以CKD格式和FBA格式存储数据的第一和第二存储装置，并且具有第一和第二通信控制 意味着分别从大型计算机和开放系统计算机接收数据输入/输出请求，以及第二存储装置，其连接到存储有CKD格式的数据的第三存储装置，并且具有连接到第二通信的第三通信装置 其中，如果从所述开放系统计算机接收到的数据读取请求用于存储在所述第三存储设备上的数据，则所述第一存储设备控制器向所述第二存储设备控制器发送命令，并且发送从所述第三存储设备读出的数据 设备由第二存储设备控制器发送到开放系统计算机。

公开(公告)号：US5657458A

公开(公告)日：1997-08-12

申请号：US480397

申请日：1995-06-07

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Hideaki Gemma ,  Tetsuhiko Okada ,  Kazuhiko Komori ,  Koichi Okazawa

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Hideaki Gemma ,  Tetsuhiko Okada ,  Kazuhiko Komori ,  Koichi Okazawa

IPC分类号： G06F13/362 ,  G06F13/00 ,  G06F13/12 ,  G06F13/364 ,  G06F13/38 ,  G06F13/42

CPC分类号： G06F13/364

摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

摘要翻译： 一种信息处理系统，其中作为执行对模块的读取访问以作为从机操作的主机的模块请求总线仲裁器以提供具有总线主控请求信号的总线主控性，并且同时断言最后一个周期 信号，以通知总线仲裁器下一个周期将是主机使用的最后一个周期的事实。 随后，当主机已经使用由总线仲裁器通过总线使用授权信号授予的总线时，它通过在下一个周期中使用总线将地址传送到从机，从而开始读取访问。 读取权限后，主人释放总线主控权。 只有当从站未能接受传送的地址时，它会在地址的传输周期不被接受的两个周期之后重新生成重试请求信号。 在这种情况下，在断言信号的周期之前执行传送两个周期的模块再次执行之前执行的传送。 因此，要传输的地址只能在一个周期内传输到模块准备好接受地址。

公开(公告)号：US5604874A

公开(公告)日：1997-02-18

申请号：US480395

申请日：1995-06-07

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Hideaki Gemma ,  Tetsuhiko Okada ,  Kazuhiko Komori ,  Koichi Okazawa

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Hideaki Gemma ,  Tetsuhiko Okada ,  Kazuhiko Komori ,  Koichi Okazawa

IPC分类号： G06F13/362 ,  G06F13/00 ,  G06F13/12 ,  G06F13/364 ,  G06F13/38 ,  G06F13/42 ,  G06F15/16

CPC分类号： G06F13/364

摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

公开(公告)号：US4774045A

公开(公告)日：1988-09-27

申请号：US837832

申请日：1986-03-10

申请人： Shizuko Kushida ,  Takashi Tsubahara ,  Takafumi Naito ,  Seiji Kaneko ,  Yasunori Matsuoka ,  Takefumi Shindo

发明人： Shizuko Kushida ,  Takashi Tsubahara ,  Takafumi Naito ,  Seiji Kaneko ,  Yasunori Matsuoka ,  Takefumi Shindo

IPC分类号： B28B1/00 ,  E04C2/04 ,  B28B1/16 ,  B29C39/12

CPC分类号： B28B1/008 ,  E04C2/04 ,  E04C2/044 ,  Y10S264/57

摘要： A concrete structural member of improved stability is produced by preparing a concrete composite layer having a concrete layer on one side and an aggregate layer on the other side thereof, impregnating the composite layer with a monomer, thermally or catalytically polymerizing the monomer impregnated in the composite layer, and thereafter placing fresh concrete on the aggregate layer side of the polymer-impregnated composite layer.

摘要翻译： 通过制备在一侧具有混凝土层和在另一侧上具有聚集层的混凝土复合层来制造具有改进的稳定性的混凝土结构构件，用单体浸渍复合层，将浸渍在复合材料中的单体进行热或催化聚合 然后将新拌混凝土置于聚合物浸渍的复合层的聚集层一侧。