公开(公告)号：US09083641B2

公开(公告)日：2015-07-14

申请号：US13289652

申请日：2011-11-04

Applicant: Naveen K. Jain ,  Venkata Rangavajjhala

Inventor： Naveen K. Jain ,  Venkata Rangavajjhala

IPC: H04L12/935 ,  H04L12/933

CPC classification number: H04L49/3036 ,  H04L49/103 ,  H04L49/3063

Abstract: A network processing device having multiple processing engines capable of providing multi-context parallel processing is disclosed. The device includes a receiver and a packet processor, wherein the receiver is capable of receiving packets at a predefined packet flow rate. The packet processor, in one embodiment, includes multiple processing engines, wherein each processing engine is further configured to include multiple context processing components. The context processing components are used to provide multi-context parallel processing to increase throughput.

Abstract translation: 公开了具有能够提供多上下文并行处理的多个处理引擎的网络处理装置。 该设备包括接收机和分组处理器，其中接收机能够以预定的分组流速接收分组。 在一个实施例中，分组处理器包括多个处理引擎，其中每个处理引擎还被配置为包括多个上下文处理组件。 上下文处理组件用于提供多上下文并行处理以增加吞吐量。

公开(公告)号：US08228923B1

公开(公告)日：2012-07-24

申请号：US11971427

申请日：2008-01-09

Applicant: Naveen K. Jain ,  Venkata Rangavajjhala

Inventor： Naveen K. Jain ,  Venkata Rangavajjhala

IPC: H04L12/28 ,  H04L12/56 ,  H04J3/06 ,  H04J3/00

CPC classification number: H04L47/28 ,  H04J3/0682 ,  H04L45/74

Abstract: A network device having a system performance measurement unit employing one or more global time stamps for measuring the device performance is disclosed. The device includes an ingress circuit, a global time counter, an egress circuit, and a processor. The ingress circuit is configured to receive a packet from an input port while the global time counter generates an arrival time stamp in accordance with the arrival time of the packet. The egress circuit is capable of forwarding the packet to other network devices via an output port. The processor, in one embodiment, is configured to calculate packet latency in response to the arrival time stamp.

Abstract translation: 公开了一种具有系统性能测量单元的网络设备，该单元采用一个或多个全局时间戳来测量设备性能。 该设备包括入口电路，全局时间计数器，出口电路和处理器。 入口电路被配置为在全局时间计数器根据分组的到达时间产生到达时间戳时从输入端口接收分组。 出口电路能够通过输出端口将数据包转发到其他网络设备。 在一个实施例中，处理器被配置为响应于到达时间戳来计算分组等待时间。

公开(公告)号：US08072882B1

公开(公告)日：2011-12-06

申请号：US12358865

申请日：2009-01-23

Applicant: Naveen K. Jain ,  Venkata Rangavajjhala

Inventor： Naveen K. Jain ,  Venkata Rangavajjhala

IPC: H04L12/26 ,  G06F15/16 ,  G06F13/24

CPC classification number: H04L49/103 ,  H04L49/3063

Abstract: A method and apparatus for improving packet processing employing a network flow control mechanism are disclosed. A network process, in one embodiment, suspends distribution of incoming packet(s) to one or more, packet processing engines (“PEs”) upon detecting a stalling request. After identifying currently executing operations initiated by one or more kicking circuits before the issuance of stalling request, the process allows the currently executing operations to complete despite the activation of the stalling request.

Abstract translation: 公开了一种使用网络流控制机制改进分组处理的方法和装置。 在一个实施例中，网络处理在检测到停止请求时暂停将输入分组分发到一个或多个分组处理引擎（“PE”）。 在发出停止请求之前，在识别由一个或多个踢脚电路发起的当前执行操作之后，该过程允许当前执行的操作完成，尽管停止请求的激活。