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    Distributed micro instructions set processor architecture for high-efficiency signal processing
    11.
    发明授权
    Distributed micro instructions set processor architecture for high-efficiency signal processing 有权
    分布式微指令集处理器架构，用于高效率信号处理

    公开(公告)号：US08244270B2

    公开(公告)日：2012-08-14

    申请号：US13194547

    申请日：2011-07-29

    申请人： Song Chen ,  Paul L. Chou ,  Christopher C. Woodthorpe ,  Venugopal Balasubramonian ,  Keith Rieken

    发明人： Song Chen ,  Paul L. Chou ,  Christopher C. Woodthorpe ,  Venugopal Balasubramonian ,  Keith Rieken

    IPC分类号： H04Q7/20 ,  H04W72/00

    CPC分类号： G06F15/78 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3885 ,  G06F9/462 ,  G06F9/4881 ,  Y02D10/24

    摘要： A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

    摘要翻译： 无线通信系统根据通信协议承载多个进程。 该系统包括为该过程提供计算支持的特定于应用程序的指令集处理器（ASISP）。 每个ASISP能够执行通信协议的功能的子集。 调度程序用于以时间分片算法调度ASISP，以便每个ASISP支持多个进程。 在这种体系结构中，ASISP在任何给定的时间主动执行一个受支持进程（活动进程）的计算。 由特定ASISP支持的每个进程的状态信息存储在与ASISP唯一相关联的存储体中。 当调度器指示ASISP改变哪个进程是活动进程时，将非活动进程的状态信息存储在存储体中，并且从存储体检索新激活的进程的状态信息。

    Flexible preamble processing for detecting a code sequence
    16.
    发明授权
    Flexible preamble processing for detecting a code sequence 有权
    用于检测代码序列的灵活的前导码处理

    公开(公告)号：US06694496B2

    公开(公告)日：2004-02-17

    申请号：US09922406

    申请日：2001-08-03

    申请人： Gregory R. Goslin ,  Venugopal Balasubramonian

    发明人： Gregory R. Goslin ,  Venugopal Balasubramonian

    IPC分类号： G06F1750

    CPC分类号： H04B1/7077 ,  H04B1/707 ,  H04B1/70751 ,  H04B2201/70701 ,  H04B2201/70707 ,  H04J3/0611

    摘要： An architecture and method for flexible preamble processing is disclosed herein. The preamble processing engine detects a code sequence in input, where the code sequence is a sum of a first code sequence and a second code sequence The preamble processing engine includes a data input line, a code input line, a despreader, and a plurality of memory registers. The code input selectively receives the first code sequence or the second code sequence, the first code sequence having a period longer than a period for the second code sequence. The despreader is coupled to the data input line and the code input line. The despreader producing a despread result between the first code sequence and the input data. Lastly, the plurality of memory registers, which are coupled to the despreader, each stores only a portion of the despread results.

    摘要翻译： 本文公开了用于灵活前同步码处理的架构和方法。 前导处理引擎检测输入中的代码序列，其中代码序列是第一代码序列和第二代码序列的和。前导码处理引擎包括数据输入线，代码输入线，解扩器和多个 存储器寄存器。 代码输入选择性地接收第一代码序列或第二代码序列，第一代码序列具有比第二代码序列的周期长的周期。 解扩器耦合到数据输入线和代码输入线。 解扩器在第一代码序列和输入数据之间产生解扩结果。 最后，耦合到解扩器的多个存储器寄存器每个仅存储解扩结果的一部分。

    DISTRIBUTED MICRO INSTRUCTIONS SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING
    17.
    发明申请
    DISTRIBUTED MICRO INSTRUCTIONS SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING 有权
    分布式微指令设置高效信号处理的处理器架构

    公开(公告)号：US20110314257A1

    公开(公告)日：2011-12-22

    申请号：US13194547

    申请日：2011-07-29

    申请人： Song CHEN ,  Paul L. CHOU ,  Christopher C. WOODTHORPE ,  Venugopal BALASUBRAMONIAN ,  Keith RIEKEN

    发明人： Song CHEN ,  Paul L. CHOU ,  Christopher C. WOODTHORPE ,  Venugopal BALASUBRAMONIAN ,  Keith RIEKEN

    IPC分类号： G06F15/76 ,  G06F9/06

    CPC分类号： G06F15/78 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3885 ,  G06F9/462 ,  G06F9/4881 ,  Y02D10/24

    摘要： A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

    摘要翻译： 无线通信系统根据通信协议承载多个进程。 该系统包括为该过程提供计算支持的特定于应用程序的指令集处理器（ASISP）。 每个ASISP能够执行通信协议的功能的子集。 调度程序用于以时间分片算法调度ASISP，以便每个ASISP支持多个进程。 在这种体系结构中，ASISP在任何给定的时间主动执行一个受支持进程（活动进程）的计算。 由特定ASISP支持的每个进程的状态信息存储在与ASISP唯一相关联的存储体中。 当调度器指示ASISP改变哪个进程是活动进程时，将非活动进程的状态信息存储在存储体中，并且从存储体检索新激活的进程的状态信息。

    Distributed micro instruction set processor architecture for high-efficiency signal processing
    18.
    发明授权
    Distributed micro instruction set processor architecture for high-efficiency signal processing 有权
    分布式微指令集处理器架构，用于高效率信号处理

    公开(公告)号：US08014786B2

    公开(公告)日：2011-09-06

    申请号：US11841604

    申请日：2007-08-20

    申请人： Song Chen ,  Paul L. Chou ,  Christopher C. Woodthorpe ,  Venugopal Balasubramonian ,  Keith Rieken

    发明人： Song Chen ,  Paul L. Chou ,  Christopher C. Woodthorpe ,  Venugopal Balasubramonian ,  Keith Rieken

    IPC分类号： H04Q7/20

    CPC分类号： G06F15/78 ,  G06F9/30079 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3885 ,  G06F9/462 ,  G06F9/4881 ,  Y02D10/24

    摘要： A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

    摘要翻译： 无线通信系统根据通信协议承载多个进程。 该系统包括为该过程提供计算支持的特定于应用程序的指令集处理器（ASISP）。 每个ASISP能够执行通信协议的功能的子集。 调度程序用于以时间分片算法调度ASISP，以便每个ASISP支持多个进程。 在这种体系结构中，ASISP在任何给定的时间主动执行一个受支持进程（活动进程）的计算。 由特定ASISP支持的每个进程的状态信息存储在与ASISP唯一相关联的存储体中。 当调度器指示ASISP改变哪个进程是活动进程时，将非活动进程的状态信息存储在存储体中，并且从存储体检索新激活的进程的状态信息。