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11.发明授权公开(公告)号：US06513108B1
公开(公告)日：2003-01-28
申请号：US09106478
申请日：1998-06-29
IPC分类号： G06F1516
CPC分类号： G06F15/17337 , G06F15/8023
摘要： A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.
摘要翻译： 可编程处理引擎处理计算机网络的中间网络站内的瞬态数据。 引擎包括一组处理元件，其对称地排列成行和列，并且嵌入在具有从阵列到外部存储器的多个接口的输入和输出缓冲单元之间。 外部存储器存储组织在诸如转发和路由表之类的数据结构内的非瞬态数据，用于处理瞬态数据。 每个处理元件都包含一个指令存储器，允许对阵列进行编程，以将瞬态数据作为并行运行的基线或扩展管线的处理元件级进行处理。
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12.发明授权Method and apparatus for generating error detection data for encapsulated frames 有权用于生成封装帧的错误检测数据的方法和装置公开(公告)号：US06226771B1
公开(公告)日：2001-05-01
申请号：US09211682
申请日：1998-12-14
IPC分类号： A03M1300
CPC分类号： H04L1/0061 , H03M13/09 , H04L1/0041
摘要： An error detection generator calculates error detection data for insertion into encapsulated frames. The error detection generator is configured to calculate multiple error detection values and insert them into corresponding fields of the encapsulated frames. The error detection generator includes a controller, three cyclic redundancy check (CRC) engines and at least one multiplexer. Each CRC engine is selectively enabled by the controller to calculate a frame check sequence (FCS) value on a different portion of the frame. Downstream CRC engines also receive the outputs from the upstream CRC engines so that these earlier FCS values may be used during subsequent calculations. The outputs of the CRC engines are also inserted into the appropriate fields of the encapsulated frames by the multiplexer.
摘要翻译： 错误检测生成器计算插入到封装帧中的错误检测数据。 错误检测发生器被配置为计算多个错误检测值并将其插入到封装帧的相应字段中。 误差检测发生器包括控制器，三个循环冗余校验（CRC）引擎和至少一个多路复用器。 每个CRC引擎由控制器选择性地使能以计算帧的不同部分上的帧校验序列（FCS）值。 下游CRC引擎还接收来自上游CRC引擎的输出，以便可以在随后的计算期间使用这些较早的FCS值。 CRC引擎的输出也通过多路复用器插入到封装帧的适当字段中。
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公开(公告)号：US6119215A
公开(公告)日：2000-09-12
申请号：US106246
申请日：1998-06-29
CPC分类号： G06F15/8007
摘要： A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.
摘要翻译： 用于中间网络站的阵列处理引擎的同步和控制系统包括控制处理引擎的排序电路。 处理引擎通常包括排列成并行管线的多个处理元件级。 控制系统还包括输入头缓冲器（IHB）和输出头缓冲器（OHB），后者包括用于接收由管线处理的当前瞬态数据并用于解码控制信号以确定处理数据的目的地的电路。 一个目的地是将OHB耦合到IHB的反馈路径，并将处理的数据返回到IHB，以便立即加载到可用管道中。
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14.发明授权Computer system with cascaded peripheral component interconnect (PCI) buses 失效具有级联外围组件互连（PCI）总线的计算机系统
公开(公告)号：US5632021A
公开(公告)日：1997-05-20
申请号：US547840
申请日：1995-10-25
IPC分类号： G06F13/362 , G06F13/40 , G06F13/00 , G06F13/38 , G06F13/42
CPC分类号： G06F13/4036 , G06F13/362
摘要： A system including primary and secondary PCI (Peripheral Component Interconnect) buses which do not "livelock". The system includes two PCI to PCI bridges between the primary and secondary buses. One of the bridges is configured to only act as a target on the primary bus and as a master on the secondary bus, the second bridge is configured to only act as master on the primary bus and as a target on the secondary bus. The determination of which data path is chosen is not made by the bridges and thus the bridges do not bias the direction of transmissions to one bus or to the other bus.
摘要翻译： 一种包括不“活锁”的主PCI和外部组件互连总线的系统。 该系统在主要和次要总线之间包括两个PCI到PCI桥接器。 其中一个桥被配置为仅在主总线上作为目标，并且作为辅助总线上的主站，第二桥被配置为仅在主总线上作为主站，并作为辅助总线上的目标。 选择哪个数据路径的确定不是由桥进行的，因此桥接器不将传输方向偏置到一个总线或另一个总线。
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公开(公告)号：US20110036705A1
公开(公告)日：2011-02-17
申请号：US12541262
申请日：2009-08-14
CPC分类号： G01N1/44 , B01J19/126 , B01J2219/0801 , B01J2219/0871 , B01J2219/0877 , B01J2219/089 , B01J2219/1215 , B01J2219/1233 , B01J2219/1236 , B01J2219/1242 , B01J2219/1275 , H05B6/6447 , H05B6/806
摘要： An instrument and method for high pressure microwave assisted chemistry are disclosed. The method includes the steps of applying microwave radiation to a sample in a sealed vessel while measuring the temperature of the sample and measuring the pressure generated inside the vessel and until the measured pressure reaches a designated set point, opening the vessel to release gases until the pressure inside the vessel reaches a lower designated set point, closing the vessel, and repeating the steps of opening the vessel at designated pressure set points and closing the vessel at designated pressure set points to the sample until the sample reaction reaches a designated high temperature. The designated set points can controllably differ from one another as the reaction proceeds. Microwave energy can be applied continuously or intermittently during the opening and closing steps. The apparatus includes a microwave cavity, a microwave transparent pressure resistant reaction vessel in the cavity, a cap on the reaction vessel, a pressure sensor for measuring pressure in the vessel, a temperature sensor, and means for opening and closing the cap at predetermined pressure set points measured by the pressure sensor to release pressure from the vessel.
摘要翻译： 公开了一种用于高压微波辅助化学的仪器和方法。 该方法包括以下步骤：在测量样品的温度并测量容器内部产生的压力并直到测量的压力达到指定的设定点，将微波辐射施加到密封容器中的样品中，打开容器释放气体直至 容器内的压力达到下指定设定点，关闭容器，并重复在指定压力设定点打开容器的步骤，并在指定的压力设定点关闭容器至样品，直到样品反应达到指定的高温。 当反应进行时，指定的设定点可以彼此可控地不同。 微波能量可以在打开和关闭步骤期间连续或间歇地施加。 该装置包括微波空腔，空腔中的微波透明耐压反应容器，反应容器上的盖，用于测量容器压力的压力传感器，温度传感器以及用于以预定压力打开和关闭盖的装置 由压力传感器测量的设定点以释放来自容器的压力。
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16.发明授权System for context switching between processing elements in a pipeline of processing elements 失效用于处理元素流水线中处理元素之间的上下文切换的系统
公开(公告)号：US6101599A
公开(公告)日：2000-08-08
申请号：US106244
申请日：1998-06-29
CPC分类号： G06F9/461 , G06F15/17381 , G06F9/30123 , H04L49/251 , H04L49/3063
摘要： A system and technique facilitate fast context switching among processor complex stages of a pipelined processing engine. Each processor complex comprises a central processing unit (CPU) core having a plurality of internal context switchable registers that are connected to respective registers within CPU cores of the pipelined stages by a processor bus. The technique enables fast context switching by sharing the context switchable registers between upstream and downstream CPUs to, inter alia, force program counters into the downstream registers. In one aspect of the inventive technique, the system automatically reflects (shadows) the contents of an upstream CPU's context switchable registers at respective registers of a downstream CPU over the processor bus. In another aspect of the invention, the system redirects instruction execution by the downstream CPU to an appropriate routine based on processing performed by the upstream CPU.
摘要翻译： 一种系统和技术有助于在流水线处理引擎的处理器复杂阶段之间进行快速上下文切换。 每个处理器复合体包括具有多个内部上下文可切换寄存器的中央处理单元（CPU）核心，其通过处理器总线连接到流水线级的CPU核心内的相应寄存器。 该技术通过在上游和下游CPU之间共享上下文可切换寄存器来实现快速上下文切换，特别是将程序计数器强制到下游寄存器中。 在本发明技术的一个方面，系统通过处理器总线自动反映（阴影）上游CPU上下文切换寄存器的内容到下游CPU的相应寄存器。 在本发明的另一方面，系统基于上游CPU执行的处理将下游CPU的指令执行重定向到适当的例程。
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17.发明授权System having central processor for transmitting generic packets to another processor to be altered and transmitting altered packets back to central processor for routing 失效具有中央处理器的系统，用于将通用分组传输到另一个处理器进行改变，并将改变的分组发送回中央处理器进行路由
公开(公告)号：US5490252A
公开(公告)日：1996-02-06
申请号：US954617
申请日：1992-09-30
申请人： Mario Macera , William E. Jennings , Dennis Josifovich , George W. Kajos , John A. Mastroianni , Francis E. Neil , Victor Bennett , Frank J. Bruns , Gururaj Deshpande , Jeremy Greene
发明人： Mario Macera , William E. Jennings , Dennis Josifovich , George W. Kajos , John A. Mastroianni , Francis E. Neil , Victor Bennett , Frank J. Bruns , Gururaj Deshpande , Jeremy Greene
CPC分类号： H04L12/5692 , H04L12/66 , H04L29/06 , H04L69/18
摘要： An internetworking system for exchanging packets of information between networks, the system comprising a network interface module for connecting a network to the system, receiving packets from the network in a native packet format used by the network and converting each received native packet to a packet having a generic format common to all networks connected to the system, and converting each of the generic packets to the native packet format for transmission to the network; a communication channel for carrying the generic packets to and from the network interface module, the channel having bandwidth; a first processing module for controlling dynamic allocation and deallocation of the channel bandwidth to the network connected to the system via the network interface module; and a second processing module for receiving all of the generic packets put on the channel by the network interface module, determining a destination network interface module for each of the generic packets on the channel, determining whether each of the generic packet needs to be bridged to the destination network interface module, and transmitting each of the generic packets determined to need bridging to the destination network interface module via the channel.
摘要翻译： 一种用于在网络之间交换信息包的互联网络系统，该系统包括用于将网络连接到系统的网络接口模块，以网络使用的本地分组格式从网络接收分组，并将每个接收到的本机分组转换为具有 连接到系统的所有网络通用的通用格式，以及将每个通用分组转换为本地分组格式以传输到网络; 用于将通用分组传送到网络接口模块和从网络接口模块携带的通信信道，该信道具有带宽; 第一处理模块，用于经由网络接口模块控制对连接到系统的网络的信道带宽的动态分配和释放; 以及第二处理模块，用于接收由网络接口模块放置在信道上的所有通用分组，为该信道上的每个通用分组确定目的网络接口模块，确定每个通用分组是否需要桥接到 目的地网络接口模块，并且经由信道将确定需要桥接的每个通用分组传送到目的地网络接口模块。
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18.发明授权公开(公告)号：US07144739B2
公开(公告)日：2006-12-05
申请号：US10065851
申请日：2002-11-26
申请人： William E. Jennings
发明人： William E. Jennings
CPC分类号： G01N15/1456 , G01N1/44
摘要： A pressure-sealing, pressure-monitoring closure for non-invasively sealing a reaction vessel to a defined release pressure in microwave-assisted chemistry is disclosed. The closure includes a pressure-resistant, microwave-transparent reaction vessel, one portion of which defines a mouth, a flexible pressure-transmitting releasable cover assembly on the mouth of the vessel, a pressure transducer on the cover and external to the vessel for monitoring the pressure in the vessel as exerted against the flexible cover, and a clamp for urging the vessel, the cover and the transducer together under a defined force so that when the pressure in the vessel exceeds the defined force, the cover can flex and release the pressure from the vessel.
摘要翻译： 公开了一种用于在微波辅助化学中非侵入性密封反应容器至限定释放压力的压力密封压力监测封闭件。 封闭件包括耐压微波透明的反应容器，其一部分限定了一个口，容器口上的柔性压力传递的可释放的盖组件，盖上的压力传感器和用于监测的容器的外部 容器中对柔性盖施加的压力，以及用于在限定的力下将容器，盖和换能器一起推动的夹具，使得当容器中的压力超过限定的力时，盖可以弯曲并释放 来自船只的压力。
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19.发明授权公开(公告)号：US06442669B2
公开(公告)日：2002-08-27
申请号：US09727068
申请日：2000-11-30
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译： 处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。 处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。 上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。 该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。 该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。
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