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公开(公告)号：US09237608B2
公开(公告)日：2016-01-12
申请号：US12541262
申请日：2009-08-14
CPC分类号： G01N1/44 , B01J19/126 , B01J2219/0801 , B01J2219/0871 , B01J2219/0877 , B01J2219/089 , B01J2219/1215 , B01J2219/1233 , B01J2219/1236 , B01J2219/1242 , B01J2219/1275 , H05B6/6447 , H05B6/806
摘要： An instrument and method for high pressure microwave assisted chemistry are disclosed. The method includes the steps of applying microwave radiation to a sample in a sealed vessel while measuring the temperature of the sample and measuring the pressure generated inside the vessel and until the measured pressure reaches a designated set point, opening the vessel to release gases until the pressure inside the vessel reaches a lower designated set point, closing the vessel, and repeating the steps of opening the vessel at designated pressure set points and closing the vessel at designated pressure set points to the sample until the sample reaction reaches a designated high temperature. The designated set points can controllably differ from one another as the reaction proceeds. Microwave energy can be applied continuously or intermittently during the opening and closing steps. The apparatus includes a microwave cavity, a microwave transparent pressure resistant reaction vessel in the cavity, a cap on the reaction vessel, a pressure sensor for measuring pressure in the vessel, a temperature sensor, and means for opening and closing the cap at predetermined pressure set points measured by the pressure sensor to release pressure from the vessel.
摘要翻译： 公开了一种用于高压微波辅助化学的仪器和方法。 该方法包括以下步骤：在测量样品的温度并测量容器内部产生的压力并直到测量的压力达到指定的设定点，将微波辐射施加到密封容器中的样品中，打开容器释放气体直到 容器内的压力达到下指定设定点，关闭容器，并重复在指定压力设定点打开容器的步骤，并在指定的压力设定点关闭容器至样品，直到样品反应达到指定的高温。 当反应进行时，指定的设定点可以彼此可控地不同。 微波能量可以在打开和关闭步骤期间连续或间歇地施加。 该装置包括微波空腔，空腔中的微波透明耐压反应容器，反应容器上的盖，用于测量容器压力的压力传感器，温度传感器以及用于以预定压力打开和关闭盖的装置 由压力传感器测量的设定点以释放来自容器的压力。
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2.发明授权Method and apparatus for passing data among processor complex stages of a pipelined processing engine 失效用于在流水线处理引擎的处理器复杂级之间传递数据的方法和装置公开(公告)号：US06195739B1
公开(公告)日：2001-02-27
申请号：US09106436
申请日：1998-06-29
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译： 处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。 处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。 上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。 该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。 该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。
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公开(公告)号：US20120074136A1
公开(公告)日：2012-03-29
申请号：US13239447
申请日：2011-09-22
IPC分类号： H05B6/64
CPC分类号： G01N1/44 , B01J19/126 , B01J2219/0801 , B01J2219/0871 , B01J2219/0877 , B01J2219/089 , B01J2219/1215 , B01J2219/1233 , B01J2219/1236 , B01J2219/1242 , B01J2219/1275 , H05B6/6447 , H05B6/806
摘要： An instrument and method for high pressure microwave assisted chemistry are disclosed. The method includes the steps of applying microwave radiation to a sample in a sealed vessel while measuring the temperature and pressure generated inside the vessel and until the measured pressure reaches a designated set point, opening the vessel to release gases until the pressure inside the vessel reaches a lower set point, closing the vessel, and repeating the steps of opening the vessel at designated pressure set points and closing the vessel at designated pressure set points to the sample until the sample reaction reaches a designated high temperature. Microwave energy can be applied continuously or intermittently during the opening and closing steps. Among other items, the instrument includes pressure and temperature sensors and means for opening and closing the vessel at the set points.
摘要翻译： 公开了一种用于高压微波辅助化学的仪器和方法。 该方法包括以下步骤：在测量容器内部产生的温度和压力的同时，将测量的压力达到指定的设定点，向容器中的样品施加微波辐射，打开容器释放气体，直到容器内的压力达到 下部设定点，关闭容器，并重复在指定的压力设定点打开容器的步骤，并在指定的压力设定点关闭容器至样品，直到样品反应达到指定的高温。 微波能量可以在打开和关闭步骤期间连续或间歇地施加。 在其他项目中，仪器包括压力和温度传感器以及用于在设定点打开和关闭容器的装置。
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4.发明授权公开(公告)号：US07895412B1
公开(公告)日：2011-02-22
申请号：US10184564
申请日：2002-06-27
IPC分类号： G06F15/80
CPC分类号： G06F15/17337 , G06F15/8023
摘要： A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.
摘要翻译： 可编程处理引擎处理计算机网络的中间网络站内的瞬态数据。 引擎包括一组处理元件，其对称地排列成行和列，并且嵌入在具有从阵列到外部存储器的多个接口的输入和输出缓冲单元之间。 外部存储器存储组织在诸如转发和路由表之类的数据结构内的非瞬态数据，用于处理瞬态数据。 每个处理元件都包含一个指令存储器，允许对阵列进行编程，以将瞬态数据作为并行运行的基线或扩展管线的处理元件级进行处理。
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5.发明授权Architecture for a processor complex of an arrayed pipelined processing engine 有权用于处理器阵列的流水线处理引擎的架构公开(公告)号：US07380101B2
公开(公告)日：2008-05-27
申请号：US11023283
申请日：2004-12-27
IPC分类号： G06F15/00
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译： 处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。 处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。 上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。 该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。 该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。
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公开(公告)号：US06272621B1
公开(公告)日：2001-08-07
申请号：US09642144
申请日：2000-08-18
IPC分类号： G06F1580
CPC分类号： G06F15/8007
摘要： A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.
摘要翻译： 用于中间网络站的阵列处理引擎的同步和控制系统包括控制处理引擎的排序电路。 处理引擎通常包括排列成并行管线的多个处理元件级。 控制系统还包括输入头缓冲器（IHB）和输出头缓冲器（OHB），后者包括用于接收由管线处理的当前瞬态数据并用于解码控制信号以确定处理数据的目的地的电路。 一个目的地是将OHB耦合到IHB的反馈路径，并将处理的数据返回到IHB，以便立即加载到可用管道中。
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公开(公告)号：US06182267B2
公开(公告)日：2001-01-30
申请号：US09197225
申请日：1998-11-20
IPC分类号： G06F1110
CPC分类号： G06F11/10
摘要： A system and method are provided that permit an accurate checksum to be generated of a block of data being transmitted via a prefetched bus, despite repeated transmissions of identical portions of the block and presentation of those identical to checksum logic simultaneously with their transmission by the bus, by ensuring that only those portions of the data block that have yet to be checksummed are checksummed.
摘要翻译： 提供了一种系统和方法，其允许生成经由预取总线传输的数据块的精确校验和，尽管块的相同部分的重复传输和与校验和逻辑相同的那些与其总线的传输同时呈现 通过确保只有那些尚未被校验和的数据块的那些部分被校验和。
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公开(公告)号：US06173386B2
公开(公告)日：2001-01-09
申请号：US09213291
申请日：1998-12-14
IPC分类号： G06F1516
CPC分类号： G06F11/3648
摘要： A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of the processing element complexes into a debug mode of operation. When a complex is in debug mode, examination of internal stages of the component circuits of the complex may occur, in order to facilitate debugging of software and hardware errors that may occur during operation of the processor.
摘要翻译： 提供并行处理器，包括集成的调试功能。 处理器包括流水线处理引擎，具有处理元件复杂级的阵列，以及输入和输出头缓冲器。 提供了一种调试系统，当被触发时，可以将部分或全部处理元件复合体置于调试操作模式中。 当复合体处于调试模式时，可能会发现复合体的组件电路的内部级的检查，以便于调试在处理器运行期间可能发生的软件和硬件错误。
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9.发明授权Architecture for a processor complex of an arrayed pipelined processing engine 有权用于处理器阵列的流水线处理引擎的架构公开(公告)号：US06836838B1
公开(公告)日：2004-12-28
申请号：US10222277
申请日：2002-08-16
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译： 处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。 处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。 上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。 该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。 该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。
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公开(公告)号：US06649889B2
公开(公告)日：2003-11-18
申请号：US10063914
申请日：2002-05-23
申请人： William E. Jennings
发明人： William E. Jennings
IPC分类号： H05B672
CPC分类号： H05B6/806 , B01J19/126 , B01J2219/00058 , B01J2219/00063 , B01J2219/00065 , B01J2219/00094 , B01J2219/002 , B01J2219/0024 , B01J2219/1209 , B01J2219/1233 , B01J2219/1269 , B01J2219/1275 , H01P7/06
摘要： An instrument is disclosed for microwave-assisted chemical processes that avoids tuning discrepancies that otherwise result based upon the materials being heated. The instrument includes a source of microwave radiation, a waveguide in communication with the source, with at least a portion of the waveguide forming a cylindrical arc, a cylindrical cavity immediately surrounded by the cylindrical arc portions of the waveguide, and at least three slotted openings in the circumference of the circular waveguide that provide microwave communication between the waveguide and the cavity.
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