公开(公告)号：US07327616B2

公开(公告)日：2008-02-05

申请号：US11235206

申请日：2005-09-27

Applicant: Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

Inventor： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC: G11C5/14

CPC classification number: G11C16/102

Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

Abstract translation: 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US20090303797A1

公开(公告)日：2009-12-10

申请号：US12479473

申请日：2009-06-05

Applicant: Kikuko SUGIMAE ,  Yasushi Kameda

Inventor： Kikuko SUGIMAE ,  Yasushi Kameda

IPC: G11C16/04 ,  H01L21/336 ,  H01L29/94 ,  H01L27/115

CPC classification number: G11C16/08 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/78 ,  H01L29/7831 ,  H01L29/7881

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the substrate, a first gate electrode formed on the gate insulating film, source and drain regions formed in the substrate so as to sandwich the first gate electrode, an intergate insulating film formed on the first gate electrode and including an opening, a second gate electrode formed on the intergate insulating film and electrically connected to the first gate electrode through the opening, and a boost electrode formed on the intergate insulating film and electrically isolated from the first gate electrode and the second gate electrode.

Abstract translation: 半导体器件包括半导体衬底，形成在衬底上的栅极绝缘膜，形成在栅极绝缘膜上的第一栅极电极，形成在衬底中的源极和漏极区域，以夹持第一栅电极，形成栅极间绝缘膜 在第一栅电极上并且包括开口，形成在栅间绝缘膜上并通过开口电连接到第一栅电极的第二栅电极和形成在栅间绝缘膜上并与第一栅极电隔离的升压电极 和第二栅电极。

公开(公告)号：US06307791B1

公开(公告)日：2001-10-23

申请号：US09667220

申请日：2000-09-21

Applicant: Nobuaki Otsuka ,  Yasushi Kameda

Inventor： Nobuaki Otsuka ,  Yasushi Kameda

IPC: G11C700

CPC classification number: G11C7/1057 ,  G11C7/1051

Abstract: A semiconductor device has an output buffer having transistors connected in parallel for an external driving purpose, a connection terminal connected to an external resistor, and an output impedance controller connected to the connection terminal and the output buffer, for adjusting the impedance of the output buffer in accordance with the external resistor. The output impedance controller has a first transistor of a first conductivity type having a drain connected to the connection terminal; a first level-controller connected to a gate of the first transistor, for controlling the level of the gate of the first transistor to set the connection terminal to a predetermined voltage level; a second transistor having a gate connected to the gate of the first transistor and a source connected to a source of the first transistor; a first dummy transistor group consisting of transistors that are of a second conductivity type, are connected to the second transistor, correspond to the output buffer transistors, and are connected in parallel; a first controller connected to the second transistor and the first dummy transistor group, for controlling the first dummy transistor group to equalize the level of a connection node between the second transistor and the first dummy transistor group with the predetermined voltage level; and a second controller for controlling the output buffer transistors according to the control carried out by the first controller.

Abstract translation: 半导体器件具有输出缓冲器，其具有用于外部驱动的并联连接的晶体管，连接到外部电阻器的连接端子和连接到连接端子和输出缓冲器的输出阻抗控制器，用于调整输出缓冲器的阻抗 按照外部电阻。 输出阻抗控制器具有第一导电类型的第一晶体管，其漏极连接到连接端子; 连接到第一晶体管的栅极的第一电平控制器，用于控制第一晶体管的栅极电平以将连接端子设置到预定电压电平; 第二晶体管，具有连接到第一晶体管的栅极的栅极和连接到第一晶体管的源极的源极; 由第二导电类型的晶体管组成的第一虚拟晶体管组连接到第二晶体管，对应于输出缓冲晶体管，并联连接; 连接到第二晶体管和第一虚设晶体管组的第一控制器，用于控制第一虚拟晶体管组以使具有预定电压电平的第二晶体管和第一虚拟晶体管组之间的连接节点的电平相等; 以及第二控制器，用于根据由第一控制器执行的控制来控制输出缓冲晶体管。

公开(公告)号：USRE36404E

公开(公告)日：1999-11-23

申请号：US970780

申请日：1997-11-14

Applicant: Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

Inventor： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

IPC: G11C11/41 ,  G11C8/14 ,  G11C11/40 ,  G11C7/00

CPC classification number: G11C8/14

Abstract: A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

Abstract translation: 一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。 主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。 部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。 为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。 为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑 运算结果满足规定的逻辑条件。 每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。 每个主字线连接到第一和第二逆变器的输入端。 各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。 位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

公开(公告)号：US07729178B2

公开(公告)日：2010-06-01

申请号：US11849891

申请日：2007-09-04

Applicant: Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

Inventor： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC: G11C7/10

CPC classification number: G11C16/102

Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

Abstract translation: 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US20060104117A1

公开(公告)日：2006-05-18

申请号：US11246215

申请日：2005-10-11

Applicant: Yasushi Kameda

Inventor： Yasushi Kameda

IPC: G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3459

Abstract: A clamp circuit is connected to one-side ends of first and second bit lines which are adjacent in a memory cell array and a data cache is connected to the other ends thereof. The first and second bit lines are selectively divided into plural portions by use of first and second switching elements. The data cache, clamp circuit and first and second switching elements are controlled by use of a control circuit and the bit line to which a memory cell of an address to be written is connected is precharged by use of the clamp circuit or data cache and the other bit line is shielded by the clamp circuit.

Abstract translation: 钳位电路连接到在存储单元阵列中相邻的第一和第二位线的一端，数据高速缓存与其另一端连接。 通过使用第一和第二开关元件将第一和第二位线选择性地分成多个部分。 通过使用控制电路来控制数据高速缓存，钳位电路和第一和第二开关元件，并且通过使用钳位电路或数据高速缓冲存储器将要写入的地址的存储单元连接到的位线被预充电，并且 其他位线被钳位电路屏蔽。