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    Semiconductor memory device implemented with a test circuit
    2.
    发明授权
    Semiconductor memory device implemented with a test circuit 失效
    用测试电路实现的半导体存储器件

    公开(公告)号：US06529438B1

    公开(公告)日：2003-03-04

    申请号：US09722195

    申请日：2000-11-22

    申请人： Yoichi Suzuki ,  Akihiro Mishima ,  Mitsuhiko Kosakai ,  Makoto Segawa ,  Yasuo Naruke

    发明人： Yoichi Suzuki ,  Akihiro Mishima ,  Mitsuhiko Kosakai ,  Makoto Segawa ,  Yasuo Naruke

    IPC分类号： G11C800

    CPC分类号： G11C8/10 ,  G11C29/02

    摘要： An improved semiconductor memory device capable of easily detecting the location of a defective bit line and a defective memory cell as a leakage current path for a short time is provided. A region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first large region and a remaining second large region, either of said first and second large regions being selected by simultaneously selecting a predetermined number of said column selection lines. Then, a region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first small region and a remaining second small region, said first and second small regions constituting said one of the first and second large regions, either of said first and second small regions being selected by simultaneously selecting a predetermined number of said column selection lines. For this purpose, an address signal output control circuit is provided within the semiconductor memory device. The address signal output control circuit is supplied with an address output control signal as externally given as a control signal for the purpose of selecting said row selection line by taking control of said row addressing signal in order to perform the control process as described above.

    摘要翻译： 提供一种改进的半导体存储器件，其能够容易地将缺陷位线和缺陷存储器单元的位置检测为短时间的漏电流路径。 通过检测第一大区域和剩余第二大区域中的一个来确定流过不小于预定值的漏电流的区域，通过同时选择预定数量的所述列选择线来选择所述第一和第二大区域中的任一个 。 然后，通过检测构成第一和第二大区域中的一个的第一和第二小区域的第一小区域和第二小区域中的一个来确定流过不小于预定值的漏电流的区域， 通过同时选择预定数量的所述列选择线来选择所述第一和第二小区域。 为此，在半导体存储器件内提供地址信号输出控制电路。 为了通过控制所述行寻址信号来选择所述行选择线，为了执行如上所述的控制处理，地址信号输出控制电路被提供作为外部给定的地址输出控制信号作为控制信号。

    Semiconductor memory device for use in apparatus requiring high-speed access to memory cells
    3.
    再颁专利
    Semiconductor memory device for use in apparatus requiring high-speed access to memory cells 失效
    用于需要高速存取存储器单元的设备中的半导体存储器件

    公开(公告)号：USRE36404E

    公开(公告)日：1999-11-23

    申请号：US970780

    申请日：1997-11-14

    申请人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

    发明人： Yasushi Kameda ,  Kenichi Nakamura ,  Hiroshi Takamoto ,  Takayuki Harima ,  Makoto Segawa

    IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/40 ,  G11C7/00

    CPC分类号： G11C8/14

    摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

    摘要翻译： 一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。 主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。 部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。 为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。 为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑 运算结果满足规定的逻辑条件。 每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。 每个主字线连接到第一和第二逆变器的输入端。 各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。 位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

    Semiconductor memory device and its topography
    4.
    发明授权
    Semiconductor memory device and its topography 失效
    半导体存储器件及其形貌

    公开(公告)号：US5263002A

    公开(公告)日：1993-11-16

    申请号：US713530

    申请日：1991-06-12

    申请人： Youichi Suzuki ,  Makoto Segawa

    发明人： Youichi Suzuki ,  Makoto Segawa

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  H01L27/10 ,  G11C5/06

    CPC分类号： G11C8/14 ,  G11C7/10

    摘要： In the semiconductor memory device, memory cells are divided into plural blocks; each block is further divided into plural I/O unit groups; and furthermore each I/O unit group is divided into plural small groups. The word lines provided for each small group of memory cells arranged at similar locations in each unit group are connected in common to a word line selecting line selected by a select circuit. Therefore, the number of memory cells connected to one word line can be reduced to decrease the power consumption and to increase the operating speed, without increasing the wiring capacitance and the chip size.

    摘要翻译： 在半导体存储器件中，存储单元被分成多个块; 每个块进一步分为多个I / O单元组; 此外，每个I / O单元组被分成多个小组。 为每个单元组中相似位置布置的每个小组存储单元提供的字线共同连接到由选择电路选择的字线选择线。 因此，可以减少连接到一个字线的存储单元的数量，从而降低功耗并提高工作速度，而不增加布线电容和芯片尺寸。

    Protected MOS transistor circuit
    6.
    发明授权
    Protected MOS transistor circuit 失效
    受保护的MOS晶体管电路

    公开(公告)号：US4893159A

    公开(公告)日：1990-01-09

    申请号：US219805

    申请日：1988-07-13

    申请人： Youichi Suzuki ,  Makoto Segawa ,  Shoji Ariizumi ,  Takeo Kondo ,  Fujio Masuoka

    发明人： Youichi Suzuki ,  Makoto Segawa ,  Shoji Ariizumi ,  Takeo Kondo ,  Fujio Masuoka

    IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H01L29/866 ,  H02H7/20 ,  H03F1/00 ,  H03F1/42 ,  H03F1/52

    CPC分类号： H01L27/0251

    摘要： This protected MOS transistor circuit has a p-type semiconductor substrate, VSS terminal, input MOS transistor, first resistor connected to the gate electrode of transistor, and MOS transistor which has a gate electrode connected to the VSS terminal and a current path connected between the VSS terminal and a junction of the first resistor and the gate electrode of the input MOS transistor. This protected MOS transistor circuit further has a second resistor connected in series with the first resistor, and pn-junction diode connected reversely between the VSS terminal and the junction of the first and second resistors.

    摘要翻译： 该受保护的MOS晶体管电路具有p型半导体衬底，VSS端子，输入MOS晶体管，连接到晶体管的栅电极的第一电阻器和连接到VSS端子的栅电极的MOS晶体管， VSS端子和输入MOS晶体管的第一电阻和栅电极的结。 该受保护MOS晶体管电路还具有与第一电阻器串联连接的第二电阻器，并且pn结二极管反向连接在VSS端子与第一和第二电阻器的结点之间。

    Driver circuit having a bootstrap buffer circuit
    7.
    发明授权
    Driver circuit having a bootstrap buffer circuit 失效
    具有自举缓冲电路的驱动电路

    公开(公告)号：US4549102A

    公开(公告)日：1985-10-22

    申请号：US709360

    申请日：1985-03-08

    申请人： Makoto Segawa ,  Shoji Ariizumi

    发明人： Makoto Segawa ,  Shoji Ariizumi

    IPC分类号： G11C11/417 ,  G11C8/10 ,  G11C11/418 ,  H03K19/017 ,  H03K19/094 ,  H03K17/284 ,  H03K17/30 ,  H03K19/003 ,  H03K19/096

    CPC分类号： H03K19/01714 ,  G11C11/418 ,  G11C8/10

    摘要： A drive circuit which includes a plurality of load MOS transistors coupled in series between a positive power source terminal and a node point, a plurality of drive MOS transistors coupled in parallel between a ground terminal and the node point, a static type bootstrap buffer circuit connected at the input terminal to the node point, and a gate control circuit for controlling the conduction states of the load and drive MOS transistors. The gate control circuit renders the load MOS transistors conductive, and then renders the drive MOS transistors nonconductive after the load MOS transistors are rendered fully conductive.

    摘要翻译： 一种驱动电路，包括串联在正电源端子和节点之间的多个负载MOS晶体管，并联在接地端子和节点之间的多个驱动MOS晶体管，静态型自举缓冲电路连接 在所述节点的输入端子处，以及用于控制所述负载和驱动MOS晶体管的导通状态的栅极控制电路。 栅极控制电路使负载MOS晶体管导通，然后在负载MOS晶体管变为完全导通之后使驱动MOS晶体管不导通。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4535426A

    公开(公告)日：1985-08-13

    申请号：US504157

    申请日：1983-06-14

    申请人： Shoji Ariizumi ,  Makoto Segawa ,  Fujio Masuoka

    发明人： Shoji Ariizumi ,  Makoto Segawa ,  Fujio Masuoka

    IPC分类号： G11C11/412 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/11 ,  G11C11/40

    CPC分类号： H01L27/1112 ,  Y10S257/903

    摘要： A memory device of the invention has a P type substrate, a first drain area of N type formed in the substrate, a second drain area of N type formed in the substrate close to the first drain area, and a source area of N.sup.+ type formed around the first and second drain areas so that the source area continuously surrounds the drain areas from three sides, e.g., the right, left and top sides of these areas. The combination of the closed arrangement of the drain areas and the surrounding arrangement of the source area decreases minority carriers generated around the drain areas and prevents unbalanced carrier absorption of the drain areas, thereby suppressing the occurrence of a soft error.

    摘要翻译： 本发明的存储器件具有P型衬底，形成在衬底中的N型第一漏极区域，在靠近第一漏极区域的衬底中形成的N型第二漏极区域和形成N +型源极区域 围绕第一和第二排水区域，使得源区域从三个侧面（例如这些区域的右侧，左侧和顶侧）连续地围绕排水区域。 漏极区域的封闭布置和源极区域的周围布置的组合减少了在漏极区域周围产生的少数载流子，并且防止了漏极区域的载流子吸收不平衡，从而抑制了软误差的发生。