公开(公告)号：US20100110290A1

公开(公告)日：2010-05-06

申请号：US12606181

申请日：2009-10-26

Applicant: Yi-Lin Li ,  Cheng-Yi Huang

Inventor： Yi-Lin Li ,  Cheng-Yi Huang

IPC: H04N5/06

CPC classification number: H04N5/06

Abstract: A signal processing method by adding odd and even field SYNC data for neutralized effects including the steps of receiving an odd field SYNC data of an odd field, which is different at a certain data segment when compared with an even field SYNC data of an even field, and the even field SYNC data of the even field; adding the odd field SYNC data and the even field SYNC data to neutralize the odd and even field SYNC data so as to generate a combined odd and even field SYNC data; and performing a predetermined signal processing on an input signal according to the combined odd and even field SYNC data.

Abstract translation: 一种信号处理方法，通过对中和效应添加奇数和偶数场SYNC数据，包括以下步骤：当与偶数场的偶数场SYNC数据相比时，在奇数场中接收奇数场的奇数场SYNC数据 ，偶数场的偶数SYNC数据; 将奇数场SYNC数据和偶数场SYNC数据相加以中和奇数和偶数场SYNC数据，以产生组合的奇数和偶数场SYNC数据; 并根据组合的奇数和偶数场SYNC数据对输入信号执行预定的信号处理。

公开(公告)号：US20070104265A1

公开(公告)日：2007-05-10

申请号：US11555691

申请日：2006-11-02

Applicant: Hou-Wei Lin ,  Yi-Lin Li ,  Cheng-Yi Huang ,  Kuang-Yu Yen

Inventor： Hou-Wei Lin ,  Yi-Lin Li ,  Cheng-Yi Huang ,  Kuang-Yu Yen

IPC: H03H7/30

CPC classification number: H04L25/03267 ,  H03H21/0012 ,  H03H2021/0092 ,  H04L25/0328

Abstract: An equalizer and an equalizing method for equalizing a received signal, where the received signal includes at least one primary interference and a plurality of secondary interferences. The Viterbi equalizer includes a filter module for filtering out the secondary interferences from the received signal to generate a filtered signal, a serial to parallel converter, coupled to the filter module, for generating a plurality of sequences according to the filtered signal, and a Viterbi equalizing module, coupled to the serial to parallel converter, for respectively equalizing the plurality of sequences to generate a plurality of equalized sequences. The architecture of the Viterbi equalizing module is greatly simplified thereby reducing the calculation activity of the Viterbi equalizer as well as maintaining its efficiency.

Abstract translation: 一种用于均衡接收信号的均衡器和均衡方法，其中接收信号包括至少一个主干扰和多个次干扰。 维特比均衡器包括滤波器模块，用于从接收到的信号滤除次级干扰以产生滤波信号，串联到并行转换器，耦合到滤波器模块，用于根据滤波信号产生多个序列;以及维特比 耦合到串行到并行转换器的均衡模块，用于分别均衡多个序列以产生多个均衡序列。 维特比均衡模块的架构大大简化，从而降低了维特比均衡器的计算活动以及维护维特比均衡器的效率。

公开(公告)号：US20060285616A1

公开(公告)日：2006-12-21

申请号：US11424537

申请日：2006-06-15

Applicant: Kuang-Yu Yen ,  Chien-Liang Tsai ,  Hou-Wei Lin ,  Yi-Lin Li

Inventor： Kuang-Yu Yen ,  Chien-Liang Tsai ,  Hou-Wei Lin ,  Yi-Lin Li

IPC: H04L7/00

CPC classification number: H04L7/0062

Abstract: The present invention provides a method and apparatus for correcting symbol timing of a receiver. The receiver receives a signal transmitted by a transmitter based on a symbol period. The method includes: sampling the signal with a sampling period to generate N sampled data in series, wherein the sampling period is half the symbol period; from Kth data of the N sampled data, getting M data to serve as a first data set; performing a timing recovery algorithm upon the first data set to generate a first timing metric; from (Kth+1) data of the N sampled data, getting M data to serve as a second data set; performing the timing recovery algorithm upon the second data set to generate a second timing metric; and correcting the symbol timing according to the first and second timing metrics.

Abstract translation: 本发明提供了一种用于校正接收机的符号定时的方法和装置。 接收机基于符号周期接收由发射机发送的信号。 该方法包括：以采样周期对信号进行采样，以产生N个采样数据，其中采样周期为符号周期的一半; 从N个采样数据的第K个数据中获取M个数据作为第一数据集; 在所述第一数据集上执行定时恢复算法以产生第一定时度量; 从N个采样数据的（K0> 0）数据中获取M个数据作为第二数据集; 在所述第二数据集上执行所述定时恢复算法以生​​成第二定时度量; 以及根据第一和第二定时度量校正符号定时。

公开(公告)号：US20050282872A1

公开(公告)日：2005-12-22

申请号：US11189654

申请日：2005-07-26

Applicant: Jon Hangeland ,  Minsheng Zhang ,  Yolanda Caringal ,  Denis Ryono ,  Yi-Lin Li ,  Johan Malm ,  Ye Liu ,  Neeraj Garg ,  Chris Litten ,  Ana Collazo ,  Konrad Koehler

Inventor： Jon Hangeland ,  Minsheng Zhang ,  Yolanda Caringal ,  Denis Ryono ,  Yi-Lin Li ,  Johan Malm ,  Ye Liu ,  Neeraj Garg ,  Chris Litten ,  Ana Collazo ,  Konrad Koehler

IPC: C07D233/88 ,  A61K31/381 ,  A61K31/40 ,  A61K31/41 ,  A61K31/415 ,  A61K31/4168 ,  A61K31/433 ,  A61K31/44 ,  A61K31/4409 ,  A61K31/495 ,  A61K31/55 ,  A61K45/00 ,  A61P3/04 ,  A61P3/06 ,  A61P5/14 ,  A61P9/06 ,  A61P9/10 ,  A61P17/00 ,  A61P17/02 ,  A61P17/04 ,  A61P17/06 ,  A61P19/10 ,  A61P25/24 ,  A61P27/06 ,  A61P35/00 ,  C07C235/32 ,  C07C235/34 ,  C07C235/52 ,  C07C307/06 ,  C07C311/00 ,  C07C311/51 ,  C07C323/41 ,  C07C323/59 ,  C07C323/60 ,  C07D207/09 ,  C07D207/26 ,  C07D207/27 ,  C07D211/24 ,  C07D211/34 ,  C07D211/58 ,  C07D211/60 ,  C07D211/96 ,  C07D213/38 ,  C07D213/40 ,  C07D213/74 ,  C07D223/12 ,  C07D231/38 ,  C07D233/54 ,  C07D241/04 ,  C07D257/04 ,  C07D285/06 ,  C07D285/12 ,  C07D285/125 ,  C07D285/135 ,  C07D295/13 ,  C07D295/185 ,  C07D333/20 ,  C07D333/34 ,  A61K31/426

CPC classification number: C07D207/27 ,  C07C235/32 ,  C07C235/52 ,  C07C307/06 ,  C07C311/51 ,  C07C323/41 ,  C07C323/60 ,  C07D207/09 ,  C07D211/24 ,  C07D211/34 ,  C07D211/58 ,  C07D211/96 ,  C07D213/40 ,  C07D223/12 ,  C07D231/38 ,  C07D233/64 ,  C07D257/04 ,  C07D285/06 ,  C07D285/135 ,  C07D295/13 ,  C07D295/185 ,  C07D333/20

Abstract: New thyroid receptor ligands are provided which have general formula (I) in which: n is an integer from 0 to 4; R1 is halogen, trifluoromethyl, or alkyl of 1 to 6 carbons or cycloalkyl of 3 to 7 carbons; R2 and R3 are the same or differential hydrogen, halogen, alkyl of 1 to 4 carbons or cycloalkyl of 3 to 5 carbons, at least one of R2 and R3 being other than hydrogen; R4 is a carboxylic acid thereof; or when n is equal to or greater than one, R4 may be heteroaromatic moiety which may be substituted or unsubstituted, or an amine (NR′R″). R5 is hydrogen or an acyl (such as acetyl or benzoyl) or other group capable of bioconversion to generate the free phenol structure (wherein R5—H). In addition, a method is provided for preventing, inhibiting or treating a disease associated with metabolism dysfunction or which is dependant upon the expression of a T3 regulated gene, wherein a compound as described above is administered in a therapeutically effective amount. Examples of such diseases associated with metabolism dysfunction or are dependent upon the expression of a T3 regulated gene include obesity, hypercholesterolemia, atherosclerosis, cardiac arrhythmias, depression, osteoporosis, hypothyroidism, goiter, thyroid cancer as well as glaucoma, congestive heart failure and skin disorders.

Abstract translation: 提供了具有通式（I）的新甲状腺受体配体，其中：n为0至4的整数; R 1是卤素，三氟甲基或1至6个碳的烷基或3至7个碳的环烷基; R 2和R 3是相同或不同的氢，卤素，1至4个碳的烷基或3至5个碳的环烷基，R 1， 2和R 3不是氢; R 4是其羧酸; 或当n等于或大于1时，R 4可以是可被取代或未取代的杂芳族部分，或胺（NR'R“）。 R 5是氢或酰基（如乙酰基或苯甲酰基）或能够生物转化以产生游离酚结构的其它基团（其中R 5 -H）。 此外，提供了一种用于预防，抑制或治疗与代谢功能障碍相关的疾病或依赖于T 3 N调节基因的表达的方法，其中如上所述的化合物以 治疗有效量。 与代谢功能障碍相关或依赖于T 3受体基因表达的这种疾病的实例包括肥胖症，高胆固醇血症，动脉粥样硬化，心律失常，抑郁症，骨质疏松症，甲状腺机能减退，甲状腺肿，甲状腺癌以及 青光眼，充血性心力衰竭和皮肤疾病。

公开(公告)号：US20050078746A1

公开(公告)日：2005-04-14

申请号：US10709462

申请日：2004-05-07

Applicant: Hou-Wei Lin ,  Shieh-Hsing Kuo ,  Yi-Lin Li ,  Kuang-Yu Yen

Inventor： Hou-Wei Lin ,  Shieh-Hsing Kuo ,  Yi-Lin Li ,  Kuang-Yu Yen

IPC: H03K5/159 ,  H04L25/03 ,  H04L25/06

CPC classification number: H04L25/03057 ,  H04L25/061 ,  H04L2025/0349

Abstract: A signal processing device for processing a passband signal to generate an equalized signal includes a passband adaptive equalizer for generating the equalized signal according to the passband signal, including at least one feed-forward equalizer (FFE) and one feedback equalizer (FBE), and a multilevel quantizer coupled with the passband adaptive equalizer for selectively utilizing a single predetermined threshold or a plurality of multiple predetermined thresholds to quantize the equalized signal in order to generate a sliced signal.

Abstract translation: 用于处理通带信号以产生均衡信号的信号处理装置包括通带自适应均衡器，用于根据通带信号产生包括至少一个前馈均衡器（FFE）和一个反馈均衡器（FBE）的均衡信号，以及 与通带自适应均衡器耦合的多电平量化器，用于选择性地利用单个预定阈值或多个多个预定阈值来量化均衡信号以产生分片信号。

公开(公告)号：US08938486B2

公开(公告)日：2015-01-20

申请号：US13431921

申请日：2012-03-27

Applicant: Yi-Lin Li

Inventor： Yi-Lin Li

IPC: G06F7/487 ,  G06F7/48

CPC classification number: G06F7/4806

Abstract: A complex divider utilized for dividing a first complex number by a second complex number to generate a computing result includes a computing unit and a dividing unit. The computing unit is utilized for receiving the first complex value and the second complex value, generating a third complex value according to the first complex value and the second complex value, and generating a real number according to the second complex value. The dividing unit is coupled to the computing unit, and is utilized for receiving the third complex value and the real number and dividing the third complex value by the real number to obtain the computing result.

Abstract translation: 用于将第一复数除以第二复数以产生计算结果的复数分频器包括计算单元和分割单元。 计算单元用于接收第一复数值和第二复数值，根据第一复数值和第二复数值产生第三复数值，并根据第二复数值生成实数。 分割单元耦合到计算单元，并用于接收第三复数值和实数，并将第三复数值除以实数以获得计算结果。

公开(公告)号：US08792544B2

公开(公告)日：2014-07-29

申请号：US13563753

申请日：2012-08-01

Applicant: Yi-Lin Li

Inventor： Yi-Lin Li

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03267

Abstract: An equalization device is arranged for equalizing a received signal, wherein the received signal may include a primary signal and at least one interference signal. The equalization device may include a transformation module, a serial-to-parallel converter, and an equalization module, wherein the transformation module may include a predictive decision feed-back equalizer, a first feed-back filter and an adder. The transformation module is arranged for generating a transformation signal according to the primary signal and the at least one interference signal of the received signal, wherein the transformation signal includes a transformed primary signal and at least one transformed interference signal. The serial-to-parallel converter is arranged for respectively converting the transformed primary signal and the transformed interference signal into a plurality of transformation signal sequences. The equalization module is arranged for respectively equalizing the plurality of transformation signal sequences so as to generate a plurality of equalized sequences.

Abstract translation: 均衡装置被布置用于均衡接收的信号，其中所接收的信号可以包括主信号和至少一个干扰信号。 均衡设备可以包括变换模块，串并转换器和均衡模块，其中变换模块可以包括预测判决反馈均衡器，第一反馈滤波器和加法器。 变换模块被配置为根据接收信号的主信号和至少一个干扰信号产生变换信号，其中变换信号包括变换的初级信号和至少一个经变换的干扰信号。 串行到并行转换器被布置为分别将变换的主信号和变换的干扰信号转换为多个变换信号序列。 均衡模块被布置用于分别均衡多个变换信号序列，以便产生多个相等的序列。

公开(公告)号：US08537281B2

公开(公告)日：2013-09-17

申请号：US12606181

申请日：2009-10-26

Applicant: Yi-Lin Li ,  Cheng-Yi Huang

Inventor： Yi-Lin Li ,  Cheng-Yi Huang

IPC: H04N5/06

CPC classification number: H04N5/06

Abstract: A signal processing method by adding odd and even field SYNC data for neutralized effects including the steps of receiving an odd field SYNC data of an odd field, which is different at a certain data segment when compared with an even field SYNC data of an even field, and the even field SYNC data of the even field; adding the odd field SYNC data and the even field SYNC data to neutralize the odd and even field SYNC data so as to generate a combined odd and even field SYNC data; and performing a predetermined signal processing on an input signal according to the combined odd and even field SYNC data.

Abstract translation: 一种信号处理方法，通过对中和效应添加奇数和偶数场SYNC数据，包括以下步骤：当与偶数场的偶数场SYNC数据相比时，在奇数场中接收奇数场的奇数场SYNC数据 ，偶数场的偶数SYNC数据; 将奇数场SYNC数据和偶数场SYNC数据相加以中和奇数和偶数场SYNC数据，以产生组合的奇数和偶数场SYNC数据; 并根据组合的奇数和偶数场SYNC数据对输入信号执行预定的信号处理。

公开(公告)号：US20120254276A1

公开(公告)日：2012-10-04

申请号：US13431921

申请日：2012-03-27

Applicant: Yi-Lin Li

Inventor： Yi-Lin Li

IPC: G06F7/535

CPC classification number: G06F7/4806

Abstract: A complex divider utilized for dividing a first complex number by a second complex number to generate a computing result includes a computing unit and a dividing unit. The computing unit is utilized for receiving the first complex value and the second complex value, generating a third complex value according to the first complex value and the second complex value, and generating a real number according to the second complex value. The dividing unit is coupled to the computing unit, and is utilized for receiving the third complex value and the real number and dividing the third complex value by the real number to obtain the computing result.

Abstract translation: 用于将第一复数除以第二复数以产生计算结果的复数分频器包括计算单元和分割单元。 计算单元用于接收第一复数值和第二复数值，根据第一复数值和第二复数值产生第三复数值，并根据第二复数值生成实数。 分割单元耦合到计算单元，并用于接收第三复数值和实数，并将第三复数值除以实数以获得计算结果。

公开(公告)号：US20100091830A1

公开(公告)日：2010-04-15

申请号：US12578555

申请日：2009-10-13

Applicant: Yi-Lin Li ,  Cheng-Yi Huang

Inventor： Yi-Lin Li ,  Cheng-Yi Huang

IPC: H03H7/30

CPC classification number: H04B3/142 ,  H04L25/03063 ,  H04L25/03292

Abstract: An equalizer includes a tapped delay line and an adder. The tapped delay line includes a plurality of taps cascaded to each other. The tapped delay line receives an input signal, a plurality of tap control signals, and a plurality of tap coefficients and generates a plurality of multiplied signals. The plurality of taps is divided into a plurality of groups. The adder is coupled to the tapped delay line for adding the plurality of multiplied signals up to generate an output signal.

Abstract translation: 均衡器包括抽头延迟线和加法器。 抽头延迟线包括彼此级联的多个抽头。 抽头延迟线接收输入信号，多个抽头控制信号和多个抽头系数，并产生多个相乘的信号。 多个抽头被分成多个组。 加法器耦合到抽头延迟线，用于将多个相乘信号加上以产生输出信号。