公开(公告)号：US20140245109A1

公开(公告)日：2014-08-28

申请号：US14273901

申请日：2014-05-09

申请人： Yong-Tae YIM ,  Sung-Kue JO

发明人： Yong-Tae YIM ,  Sung-Kue JO

IPC分类号： G06F11/10

CPC分类号： G06F11/1658 ,  G06F3/0616 ,  G06F3/0619 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/7211 ,  G11C16/349 ,  G11C16/3495

摘要： Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

摘要翻译： 提供了一种记忆系统和磨损均衡方法。 存储器系统包括闪存器件和存储器控制器。 闪速存储器件包括多个存储块，每个存储块包括多个存储单元。 存储器控制器被配置为基于每个存储器块的擦除事件信息和错误检查和校正（ECC）事件信息来控制闪速存储器件，使得存储块的使用更均匀地分布。

公开(公告)号：US08522114B2

公开(公告)日：2013-08-27

申请号：US12768047

申请日：2010-04-27

申请人： Woo tae Chang ,  Yong tae Yim

发明人： Woo tae Chang ,  Yong tae Yim

IPC分类号： G11C29/00

CPC分类号： G06F11/1048

摘要： A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory.

摘要翻译： 提供了一种存储系统。 存储器系统包括非易失性存储器和控制器。 非易失性存储器包括存储单元阵列和被配置为在读取操作期间在存储单元阵列中执行读/写操作的读/写电路。 控制器被配置为从非易失性存储器接收读取的数据，对读取的数据执行错误检测和校正操作。 在检测到所读取的数据的接收部分中的错误时，控制器还被配置为停止从非易失性存储器进一步发送读取的数据，对读取的数据的接收部分执行错误检测和校正操作，以校正检测到的 错误。 在读取数据的接收部分中校正检测到的错误之后，控制器被配置为恢复从非易失性存储器发送读取的数据。

公开(公告)号：US20120072810A1

公开(公告)日：2012-03-22

申请号：US13239534

申请日：2011-09-22

申请人： Yong-Tae YIM ,  Yun-Ho CHOI

发明人： Yong-Tae YIM ,  Yun-Ho CHOI

IPC分类号： H03M13/07 ,  G06F11/10

CPC分类号： G11C7/1006 ,  G06F11/1008 ,  G11C2029/0411 ,  G11C2207/104

摘要： An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type.

摘要翻译： 提供了纠错电路，误差校正方法以及包括误差校正电路的半导体存储器件。 误差校正电路包括部分校正子发生器，第一和第二误差位置检测器，系数计算器和确定器。 部分综合征发生器使用编码数据计算至少两个部分综合征。 第一误差位置检测器使用部分综合征的一部分来计算第一误差位置。 系数计算器使用至少两个部分综合征计算误差位置方程的系数。 确定器基于系数确定错误类型。 第二错误位置检测器可选地基于错误类型计算第二错误位置。

公开(公告)号：US20110296131A1

公开(公告)日：2011-12-01

申请号：US13117352

申请日：2011-05-27

申请人： Yong Tae YIM ,  Won Moon CHEON ,  Jin Yeong KIM ,  Du-Won HONG ,  Jong-Min KIM

发明人： Yong Tae YIM ,  Won Moon CHEON ,  Jin Yeong KIM ,  Du-Won HONG ,  Jong-Min KIM

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7205

摘要： A memory controller includes a microprocessor, a queue configured to store a plurality of first commands provided by the microprocessor, a queue management block configured to interpret and control said plurality of first commands, and a command generator configured to provide a plurality of second commands under control of the queue management block. The queue management block may simultaneously perform the plurality of second commands so as to simultaneously access a plurality of non-volatile memory units.

摘要翻译： 存储器控制器包括微处理器，被配置为存储由微处理器提供的多个第一命令的队列，被配置为解释和控制所述多个第一命令的队列管理块，以及命令生成器，被配置为提供多个第二命令， 控制队列管理块。 队列管理块可以同时执行多个第二命令，以便同时访问多个非易失性存储器单元。

公开(公告)号：US20100281342A1

公开(公告)日：2010-11-04

申请号：US12768047

申请日：2010-04-27

申请人： Woo tae CHANG ,  Yong tae YIM

发明人： Woo tae CHANG ,  Yong tae YIM

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1048

摘要： A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory.

摘要翻译： 提供了一种存储系统。 存储器系统包括非易失性存储器和控制器。 非易失性存储器包括存储单元阵列和被配置为在读取操作期间在存储单元阵列中执行读/写操作的读/写电路。 控制器被配置为从非易失性存储器接收读取的数据，对读取的数据执行错误检测和校正操作。 在检测到所读取的数据的接收部分中的错误时，控制器还被配置为停止从非易失性存储器进一步发送读取的数据，对读取的数据的接收部分执行错误检测和校正操作，以校正检测到的 错误。 在读取数据的接收部分中校正检测到的错误之后，控制器被配置为恢复从非易失性存储器发送读取的数据。

公开(公告)号：US20090049364A1

公开(公告)日：2009-02-19

申请号：US12190855

申请日：2008-08-13

申请人： Sung-Kyu JO ,  Yong-Tae YIM

发明人： Sung-Kyu JO ,  Yong-Tae YIM

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/356 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5641 ,  H03M13/098 ,  H03M13/13 ,  H03M13/6306

摘要： Disclosed are program and read methods for a nonvolatile memory system, including determining to program first data in which one of fast and normal modes; providing the first data with an error code generated by a multi-bit ECC engine, in the fast mode, and generating second data; programming the second data in a cell array by a program voltage having a second start level higher than a first start level; and reading the second data from the cell array, the second data being output after processed by the multi-bit ECC engine that detects and corrects an error from the second data.

摘要翻译： 公开了一种用于非易失性存储器系统的程序和读取方法，包括：确定编程快速和正常模式之一的第一数据; 在快速模式下向第一数据提供由多位ECC引擎产生的错误代码，并产生第二数据; 通过具有高于第一开始电平的第二起始电平的编程电压对单元阵列中的第二数据进行编程; 以及从所述单元阵列读取所述第二数据，所述第二数据在由所述多位ECC引擎处理之后输出，所述多位ECC引擎检测并修正来自所述第二数据的错误。