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公开(公告)号：US20240095184A1
公开(公告)日：2024-03-21
申请号：US17949716
申请日：2022-09-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Anthony Thomas Gutierrez
IPC: G06F12/1027 , G06F12/0882
CPC classification number: G06F12/1027 , G06F12/0882
Abstract: Address translation service management techniques are described. These techniques are based on metadata that is usable to provide a hint as insight into memory access, and based on this, use of a translation lookaside buffer is optimized to control which entries are maintained in the queue and manage address translation requests.
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12.发明公开公开(公告)号：US20230315536A1
公开(公告)日：2023-10-05
申请号：US17708021
申请日：2022-03-30
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mark Wyse , Bradford Michael Beckmann , John Kalamatianos , Anthony Thomas Gutierrez
IPC: G06F9/50
CPC classification number: G06F9/5077
Abstract: To reduce inter- and intra-instruction register bank access conflicts in parallel processors, a processing system includes a remapping circuit to dynamically remap virtual registers to physical registers of a parallel processor during execution of a wavefront. The remapping circuit remaps virtual registers to physical registers at a register mapping table that holds the current set of virtual to physical register mappings based on a list of available registers indicating which physical registers are available for a new mapping and a register mapping policy.
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公开(公告)号：US10318344B2
公开(公告)日：2019-06-11
申请号：US15649312
申请日：2017-07-13
Applicant: Advanced Micro Devices, Inc.
Inventor： Anthony Thomas Gutierrez
Abstract: Systems, apparatuses, and methods for predicting page migration granularities for phases of an application executing on a non-uniform memory access (NUMA) system architecture are disclosed herein. A system with a plurality of processing units and memory devices executes a software application. The system identifies a plurality of phases of the application based on one or more characteristics (e.g., memory access pattern) of the application. The system predicts which page migration granularity will maximize performance for each phase of the application. The system performs a page migration at a first page migration granularity during a first phase of the application based on a first prediction. The system performs a page migration at a second page migration granularity during a second phase of the application based on a second prediction, wherein the second page migration granularity is different from the first page migration granularity.
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公开(公告)号：US20190018705A1
公开(公告)日：2019-01-17
申请号：US15649312
申请日：2017-07-13
Applicant: Advanced Micro Devices, Inc.
Inventor： Anthony Thomas Gutierrez
Abstract: Systems, apparatuses, and methods for predicting page migration granularities for phases of an application executing on a non-uniform memory access (NUMA) system architecture are disclosed herein. A system with a plurality of processing units and memory devices executes a software application. The system identifies a plurality of phases of the application based on one or more characteristics (e.g., memory access pattern) of the application. The system predicts which page migration granularity will maximize performance for each phase of the application. The system performs a page migration at a first page migration granularity during a first phase of the application based on a first prediction. The system performs a page migration at a second page migration granularity during a second phase of the application based on a second prediction, wherein the second page migration granularity is different from the first page migration granularity.
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公开(公告)号：US20250077307A1
公开(公告)日：2025-03-06
申请号：US18240692
申请日：2023-08-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Ali Arda Eker , Martha Massee Barker , Anthony Thomas Gutierrez
Abstract: In accordance with the described techniques, a command processor processes a fiber graph that includes fibers each having one or more tasks and indicates dependencies between the fibers and between tasks within the fibers. As part of this, the command processor dispatches a task from a fiber for execution by a processing element array based on the fiber being enqueued in a ready queue and the dependencies of the task being resolved. While the task is dispatched and unexecuted by the processing element array, the command processor enqueues the fiber in a sleep queue. Further, the command processor enqueues the fiber in a check queue based on the one or more tasks of the fiber having been executed by the processing element array. Based on the fiber being in the check queue, the command processor enqueues a dependent fiber in the ready queue that depends from the fiber.
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Patent Agency Ranking
公开(公告)号：US20250004949A1
公开(公告)日：2025-01-02
申请号：US18217291
申请日：2023-06-30
Applicant: Advanced Micro Devices, Inc , ATI Technologies ULC
Inventor： Paul Blinzer , Anthony Asaro , Nippon HarshadKumar Raval , Anthony Thomas Gutierrez , Leopold Grinberg , Millind Mittal , Samuel Richard Bayliss
IPC: G06F12/1009 , G06F12/14
Abstract: In accordance with the described techniques for extended attributes for shared page tables, a device includes an accelerator device and a memory management unit that maintains a first set of page tables and a second set of page tables. The second set of page tables includes extended attributes for accessing data that the accelerator device operates on. The memory management unit is configured to receive a virtual memory address, and translate the virtual memory address to a physical memory address using the first set of page tables. In addition, the memory management unit retrieves the extended attributes from the second set of page tables. In this way, data is accessed from the physical memory address based on the extended attributes.
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公开(公告)号：US12105957B2
公开(公告)日：2024-10-01
申请号：US18087964
申请日：2022-12-23
Applicant: Advanced Micro Devices, Inc.
Inventor： John Kalamatianos , Karthik Ramu Sangaiah , Anthony Thomas Gutierrez
CPC classification number: G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673
Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.
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公开(公告)号：US11816490B2
公开(公告)日：2023-11-14
申请号：US17550878
申请日：2021-12-14
Applicant: Advanced Micro Devices, Inc.
CPC classification number: G06F9/3853 , G06F1/189 , G06F9/30145 , G06F9/3885
Abstract: VLIW directed Power Management is described. In accordance with described techniques, a program is compiled to generate instructions for execution by a very long instruction word machine. During the compiling, power configurations for the very long instruction word machine to execute the instructions are determined, and fields of the instructions are populated with the power configurations. In one or more implementations, an instruction that includes a power configuration for the very long instruction word machine and operations for execution by the very long instruction word machine is obtained. A power setting of the very long instruction word machine is adjusted based on the power configuration of the instruction, and the operations of the instruction are executed by the very long instruction word machine.
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公开(公告)号：US20220092725A1
公开(公告)日：2022-03-24
申请号：US17030852
申请日：2020-09-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Brian D. Emberling , Joseph Lee Greathouse , Anthony Thomas Gutierrez
Abstract: Systems, apparatuses, and methods for implementing register compaction with early release are disclosed. A processor includes at least a command processor, a plurality of compute units, a plurality of registers, and a control unit. Registers are statically allocated to wavefronts by the control unit when wavefronts are launched by the command processor on the compute units. In response to determining that a first set of registers, previously allocated to a first wavefront, are no longer needed, the first wavefront executes an instruction to release the first set of registers. The control unit detects the executed instruction and releases the first set of registers to the available pool of registers to potentially be used by other wavefronts. Then, the control unit can allocate the first set of registers to a second wavefront for use by threads of the second wavefront while the first wavefront is still active.
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公开(公告)号：US20190187964A1
公开(公告)日：2019-06-20
申请号：US15848476
申请日：2017-12-20
Applicant: Advanced Micro Devices, Inc.
IPC: G06F8/41
CPC classification number: G06F8/4434 , G06F8/433
Abstract: Systems, apparatuses, and methods for converting computer program source code from a first high level language to a functionally equivalent executable program code. Source code in a first high level language is analyzed by a code compilation tool. In response to identifying a potential bank conflict in a multi-bank register file, operands of one or more instructions are remapped such that they map to different physical banks of the multi-bank register file. Identifying a potential bank conflict comprises one or more of identifying an intra-instruction bank conflict, an inter-instruction bank conflict, and identifying a multi-word operand with a potential bank conflict.
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