公开(公告)号：US11507519B2

公开(公告)日：2022-11-22

申请号：US17135325

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jagadish B. Kotra ,  Gabriel H. Loh ,  Matthew R. Poremba

IPC: G06F12/00 ,  G06F12/1045 ,  G09C1/00 ,  G06F12/0891 ,  G06F12/1027

Abstract: A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and selectively compresses the cache lines to increase the effective storage capacity of the processing system or encrypts the cache lines to protect against vulnerabilities.

公开(公告)号：US20200081716A1

公开(公告)日：2020-03-12

申请号：US16127093

申请日：2018-09-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Adithya Yalavarti ,  John Kalamatianos ,  Matthew R. Poremba

IPC: G06F9/38 ,  G06F9/30 ,  G06F1/32

Abstract: An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.

公开(公告)号：US20140229682A1

公开(公告)日：2014-08-14

申请号：US13765813

申请日：2013-02-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: A type of conditional probability fetcher prefetches data, such as for a cache, from another memory by maintaining information relating to memory elements in a group of memory elements fetched from the second memory. The information may be an aggregate number of memory elements that have been fetched for different memory segments in the group. The information is maintained responsive to fetching one or more memory elements from a segment of memory elements in the group of memory elements. Prefetching one or more remaining memory elements in a particular segment of memory elements from the second memory into the first memory occurs when the information relating to the memory elements in the group of memory elements indicates that a prefetching condition has been satisfied.

Abstract translation: 一种类型的条件概率提取器通过维护与从第二存储器提取的一组存储器元件中的存储器元件有关的信息，从另一存储器预取诸如用于高速缓存的数据。 信息可以是已经为组中的不同存储器段获取的存储器元素的总数。 该信息是响应于从一组存储器元件中的存储器元件的段中提取一个或多个存储器元件来保持的。 当与存储元件组中的存储元件相关的信息指示已经满足预取条件时，将存储器元件的特定段中的一个或多个剩余存储元件从第二存储器预取到第一存储器中。

公开(公告)号：US20140181389A1

公开(公告)日：2014-06-26

申请号：US13724867

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  Y02D10/13

Abstract: Data caching methods and systems are provided. The data cache method loads data into an installation cache and a cache (simultaneously or serially) and returns data from the installation cache when the data has not completely loaded into the cache. The data cache system includes a processor, a memory coupled to the processor, a cache coupled to the processor and the memory and an installation cache coupled to the processor and the memory. The system is configured to load data from the memory into the installation cache and the cache (simultaneously or serially) and return data from the installation cache to the processor when the data has not completely loaded into the cache.

Abstract translation: 提供数据缓存方法和系统。 数据高速缓存方法将数据加载到安装高速缓存和高速缓存（同时或连续）中，并在数据尚未完全加载到高速缓存中时从安装高速缓存返回数据。 数据缓存系统包括处理器，耦合到处理器的存储器，耦合到处理器和存储器的高速缓存以及耦合到处理器和存储器的安装高速缓存。 该系统被配置为当数据尚未完全加载到高速缓存中时，将数据从存储器加载到安装高速缓存和高速缓存（同时或串行）中，并将数据从安装高速缓存返回到处理器。