公开(公告)号：US20210173654A1

公开(公告)日：2021-06-10

申请号：US16705023

申请日：2019-12-05

Applicant: Apple Inc.

Inventor： Deepankar Duggal ,  Kulin N. Kothari ,  Conrado Blasco ,  Muawya M. Al-Otoom

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems, apparatuses, and methods for implementing zero cycle load bypass operations are described. A system includes a processor with at least a decode unit, control logic, mapper, and free list. When a load operation is detected, the control logic determines if the load operation qualifies to be converted to a zero cycle load bypass operation. Conditions for qualifying include the load operation being in the same decode group as an older store operation to the same address. Qualifying load operations are converted to zero cycle load bypass operations. A lookup of the free list is prevented for a zero cycle load bypass operation and a destination operand of the load is renamed with a same physical register identifier used for a source operand of the store. Also, the data of the store is bypassed to the load.

公开(公告)号：US11630670B2

公开(公告)日：2023-04-18

申请号：US17382123

申请日：2021-07-21

Applicant: Apple Inc.

Inventor： Douglas C. Holman ,  Ian D. Kountanis ,  Amit Kumar ,  Muawya M. Al-Otoom

IPC: G06F9/38

Abstract: Techniques are disclosed relating to signature-based instruction prefetching. In some embodiments, processor pipeline circuitry executes a computer program that includes control transfer instructions, such that the execution follows a taken path through the computer program. First signature prefetch table circuitry indicates prefetch addresses for signatures generated using a first signature generation technique and second signature prefetch table circuitry indicates prefetch addresses for signatures generated using a second, different signature generation technique. Signature prefetch circuitry, in response to a prefetch training event, determines a first signature according to the first technique and a second signature according to the second technique and selects one but not both of the first and second signature prefetch tables to train using the first signature or the second signature.

公开(公告)号：US20210240477A1

公开(公告)日：2021-08-05

申请号：US16778939

申请日：2020-01-31

Applicant: Apple Inc.

Inventor： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Conrado Blasco ,  Haoyan Jia ,  Amit Kumar

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, an indirect branch predictor generates indirect branch predictions based on one or more register values. The register values may be the contents of registers on which the indirect branch instruction is directly or indirectly dependent for generating the branch target address, for example. In an embodiment, at least one of the registers may be a source for a load instruction, and the indirect branch may be dependent (directly or indirectly) on the target of the load. In an embodiment, the indirect branch predictor may be one of at least two indirect branch predictors in a processor. The other indirect branch predictor may be based on a fetch address, or PC, associated with the indirect branch instruction. The other indirect branch predictor may generate a first predicted target address, and the indirect branch predictor may generate a second predicted target address for the same indirect branch instruction.

公开(公告)号：US20150205725A1

公开(公告)日：2015-07-23

申请号：US14160242

申请日：2014-01-21

Applicant: APPLE INC.

Inventor： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Ronald P. Hall ,  Michael L. Karm

IPC: G06F12/08 ,  G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867 ,  G06F12/0862 ,  Y02D10/13

Abstract: Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.

Abstract translation: 公开了关于指令模式的缓存的技术。 在一些实施例中，装置包括指令高速缓存，并且被配置为通过指令处理流水线来检测指令的执行模式。 执行模式可能涉及仅在特定指令组中执行指令。 该指令可以包括多次后向控制传送和/或在该模式的一次迭代中采取的控制传送指令，而不是在该模式的另一次迭代中进行。 该设备可以被配置为将指令存储在指令高速缓存中并且从指令高速缓存中取出并执行指令。 该装置可以包括专用于预测指令高速缓存的控制传送指令的方向的分支预测器。 各种实施例可以减少与指令处理相关联的功耗。

公开(公告)号：US20250021337A1

公开(公告)日：2025-01-16

申请号：US18352351

申请日：2023-07-14

Applicant: Apple Inc.

Inventor： Muawya M. Al-Otoom ,  Niket K. Choudhary ,  Pruthivi Vuyyuru

IPC: G06F9/38

Abstract: Disclosed techniques relate to branch prediction and trace caching. A processor may include both an instruction cache and a trace cache configured to store instructions. A branch predictor may include one or more prediction tables (e.g., tagged geometric length (TAGE) tables) configured to predict directions of conditional control transfer instructions. Rather than including a separate branch predictor for branches in the trace cache, the processor may share the prediction table(s) for instruction cache and trace cache predictions. In particular, the processor may include an additional trace prediction lane configured to access the prediction table to predict a direction of a final control transfer instruction in a trace cached by the trace cache circuitry. This may advantageously provide accurate predictions with limited impacts to circuit area and power consumption, e.g., relative to a separate predictor for the trace cache.

公开(公告)号：US20250021332A1

公开(公告)日：2025-01-16

申请号：US18352309

申请日：2023-07-14

Applicant: Apple Inc.

Inventor： Niket K. Choudhary ,  Muawya M. Al-Otoom ,  Pruthivi Vuyyuru ,  Andrew H. Lin ,  Ilhyun Kim ,  Douglas C. Holman ,  Samir Dutt ,  Ronald P. Hall

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed techniques relate to trace cache circuitry configured to identify and cache traces that satisfy certain criteria. Prediction circuitry may track directions of executed control transfer instructions, including a first category of control transfer instructions that meet a first threshold bias level toward a given direction (which may be referred to as “stable”) and a second category of control transfer instructions that do not meet the first threshold bias level (which may be referred to as “unstable”). Trace cache circuitry may identify traces of instructions that satisfy a set of criteria, including: only control transfer instructions of the first category are allowed as internal control transfer instructions and a control transfer instruction in the second category is allowed only at an end of a given trace. Disclosed techniques may advantageously provide performance and power advantages of trace caching with reduced complexity, relative to certain traditional trace caches.