公开(公告)号：US20240176744A1

公开(公告)日：2024-05-30

申请号：US18438111

申请日：2024-02-09

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6032

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US11880308B2

公开(公告)日：2024-01-23

申请号：US17933603

申请日：2022-09-20

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6032

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

公开(公告)号：US20150293577A1

公开(公告)日：2015-10-15

申请号：US14251508

申请日：2014-04-11

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Michael L. Karm ,  Ian D. Kountanis ,  David J. Williamson

IPC: G06F1/32 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3844

Abstract: Techniques are disclosed relating to power reduction during execution of instruction loops. Multiple different power saving modes may be used by a processor, such as a first power saving mode after only a few loop iterations (e.g., 2-3) and a second, deeper power saving mode after a greater number of loop iterations. The first power saving mode may include keeping a branch predictor and/or other structures active, but the second power saving mode may include reducing power to the branch predictor and/or other structures. An observation mode and an instruction capture mode may also be used by a processor prior to entering a power saving mode for loop execution. Power saving modes may also be achieved during execution of complex loops having multiple backward branches (e.g., nested loops).

Abstract translation: 公开了在执行指令循环期间降低功率的技术。 处理器可以使用多种不同的功率节省模式，例如在更多数量的循环迭代之后仅仅几次循环迭代（例如2-3）和第二更深的省电模式之后的第一省电模式。 第一省电模式可以包括保持分支预测器和/或其他结构是有效的，但是第二省电模式可以包括降低分支预测器和/或其他结构的功率。 在进入用于循环执行的省电模式之前，处理器还可以使用观察模式和指令捕获模式。 在执行具有多个后向分支（例如，嵌套循环）的复杂环路时也可以实现节电模式。

公开(公告)号：US20150205725A1

公开(公告)日：2015-07-23

申请号：US14160242

申请日：2014-01-21

Applicant: APPLE INC.

Inventor： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Ronald P. Hall ,  Michael L. Karm

IPC: G06F12/08 ,  G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/3867 ,  G06F12/0862 ,  Y02D10/13

Abstract: Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.

Abstract translation: 公开了关于指令模式的缓存的技术。 在一些实施例中，装置包括指令高速缓存，并且被配置为通过指令处理流水线来检测指令的执行模式。 执行模式可能涉及仅在特定指令组中执行指令。 该指令可以包括多次后向控制传送和/或在该模式的一次迭代中采取的控制传送指令，而不是在该模式的另一次迭代中进行。 该设备可以被配置为将指令存储在指令高速缓存中并且从指令高速缓存中取出并执行指令。 该装置可以包括专用于预测指令高速缓存的控制传送指令的方向的分支预测器。 各种实施例可以减少与指令处理相关联的功耗。

公开(公告)号：US10552323B1

公开(公告)日：2020-02-04

申请号：US16126812

申请日：2018-09-10

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Todd A. Venton ,  Jonathan Y. Tong ,  David E. Kroesche

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0891 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0866

Abstract: Various embodiments of a method and apparatus for flushing a cache are disclosed. In a system, a cache memory is accessible by an execution circuit. The execution circuit executes instructions and may utilize data and/or instructions stored in the cache. A flush circuit is also coupled to the cache. Responsive to execution of a power down instruction by the execution circuit, the flush circuit performs a cache flush. If a control state is asserted in a control register, the flush circuit generates a dummy event upon completing the cache flush. Responsive to generating the dummy event, a processor core that includes the execution circuit is inhibited from being powered down.

公开(公告)号：US09311098B2

公开(公告)日：2016-04-12

申请号：US13888551

申请日：2013-05-07

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Conrado Blasco-Allue

IPC: G06F12/00 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3806 ,  G06F9/3838 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A mechanism for reducing power consumption of a cache memory of a processor includes a processor with a cache memory that stores instruction information for one or more instruction fetch groups fetched from a system memory. The cache memory may include a number of ways that are each independently controllable. The processor also includes a way prediction unit. The way prediction unit may enable, in a next execution cycle, a given way within which instruction information corresponding to a target of a next branch instruction is stored in response to a branch taken prediction for the next branch instruction. The way prediction unit may also, in response to the branch taken prediction for the next branch instruction, enable, one at a time, each corresponding way within which instruction information corresponding to respective sequential instruction fetch groups that follow the next branch instruction are stored.

Abstract translation: 用于降低处理器的高速缓冲存储器的功耗的机构包括具有高速缓存存储器的处理器，该高速缓冲存储器存储从系统存储器取出的一个或多个指令获取组的指令信息。 高速缓冲存储器可以包括各自独立可控的多种方式。 处理器还包括方式预测单元。 方式预测单元可以在下一个执行周期中使得响应于下一个分支指令的分支采取预测而存储对应于下一分支指令的目标的指令信息的给定方式。 方式预测单元还可以响应于对下一个分支指令的分支采取的预测，一次一个地使能存储与下一个分支指令之后的各个顺序指令获取组对应的指令信息的每个对应方式。

公开(公告)号：US20140337605A1

公开(公告)日：2014-11-13

申请号：US13888551

申请日：2013-05-07

Applicant: APPLE INC.

Inventor： Ronald P. Hall ,  Conrado Blasco-Allue

IPC: G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/3838 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A mechanism for reducing power consumption of a cache memory of a processor includes a processor with a cache memory that stores instruction information for one or more instruction fetch groups fetched from a system memory. The cache memory may include a number of ways that are each independently controllable. The processor also includes a way prediction unit. The way prediction unit may enable, in a next execution cycle, a given way within which instruction information corresponding to a target of a next branch instruction is stored in response to a branch taken prediction for the next branch instruction. The way prediction unit may also, in response to the branch taken prediction for the next branch instruction, enable, one at a time, each corresponding way within which instruction information corresponding to respective sequential instruction fetch groups that follow the next branch instruction are stored.

Abstract translation: 用于降低处理器的高速缓冲存储器的功耗的机构包括具有高速缓存存储器的处理器，该高速缓冲存储器存储从系统存储器取出的一个或多个指令获取组的指令信息。 高速缓冲存储器可以包括各自独立可控的多种方式。 处理器还包括方式预测单元。 方式预测单元可以在下一个执行周期中使得响应于下一个分支指令的分支采取预测而存储对应于下一分支指令的目标的指令信息的给定方式。 方式预测单元还可以响应于对下一个分支指令的分支采取的预测，一次一个地使能存储与下一个分支指令之后的各个顺序指令获取组对应的指令信息的每个对应方式。

公开(公告)号：US20250021332A1

公开(公告)日：2025-01-16

申请号：US18352309

申请日：2023-07-14

Applicant: Apple Inc.

Inventor： Niket K. Choudhary ,  Muawya M. Al-Otoom ,  Pruthivi Vuyyuru ,  Andrew H. Lin ,  Ilhyun Kim ,  Douglas C. Holman ,  Samir Dutt ,  Ronald P. Hall

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed techniques relate to trace cache circuitry configured to identify and cache traces that satisfy certain criteria. Prediction circuitry may track directions of executed control transfer instructions, including a first category of control transfer instructions that meet a first threshold bias level toward a given direction (which may be referred to as “stable”) and a second category of control transfer instructions that do not meet the first threshold bias level (which may be referred to as “unstable”). Trace cache circuitry may identify traces of instructions that satisfy a set of criteria, including: only control transfer instructions of the first category are allowed as internal control transfer instructions and a control transfer instruction in the second category is allowed only at an end of a given trace. Disclosed techniques may advantageously provide performance and power advantages of trace caching with reduced complexity, relative to certain traditional trace caches.

公开(公告)号：US11893413B2

公开(公告)日：2024-02-06

申请号：US17143149

申请日：2021-01-06

Applicant: Apple Inc.

Inventor： Michael D. Snyder ,  Ronald P. Hall ,  Deepak Limaye ,  Brett S. Feero ,  Rohit K. Gupta

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/467 ,  G06F9/5016 ,  G06F9/5022

Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

公开(公告)号：US11487667B1

公开(公告)日：2022-11-01

申请号：US17397429

申请日：2021-08-09

Applicant: Apple Inc.

Inventor： Ronald P. Hall ,  Mary D. Brown ,  Balaji Kadambi ,  Mahesh K. Reddy

IPC: G06F12/0862

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.