公开(公告)号：US20150052325A1

公开(公告)日：2015-02-19

申请号：US13969277

申请日：2013-08-16

Applicant: ARM Limited

Inventor： Hakan Persson ,  Sean Tristram Ellis

IPC: G06F12/14

CPC classification number: G06F12/1458 ,  G06F12/1433

Abstract: A data processing system includes a host processor and a graphics processing unit operable to process data under the control of an operating system executing on the host processor. The graphics processing unit can be switched between a normal mode of operation in which the it has read and write access to data that is stored in non-protected memory regions 9 but no or write-only access to any protected memory regions 8, and a protected mode of operation in which it has read and write access to data that is stored in protected memory regions 8 but only has read-only access to any non-protected memory regions 9. The data processing system further comprises a mechanism for switching the graphics processing unit from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

Abstract translation: 数据处理系统包括主处理器和图形处理单元，其可操作以在主机处理器上执行的操作系统的控制下处理数据。 图形处理单元可以在正常操作模式之间切换，在正常操作模式中，它具有对存储在非保护存储器区域9中的数据的读取和写入访问，但是对任何受保护的存储器区域8是无写入访问， 受保护的操作模式，其具有对存储在受保护的存储器区域8中的数据的读取和写入访问，但是仅具有对任何未受保护的存储器区域9的只读访问。数据处理系统还包括用于切换图形的机制 处理单元从其正常操作模式到保护操作模式，以及从其保护操作模式到正常操作模式。

公开(公告)号：US09678781B2

公开(公告)日：2017-06-13

申请号：US14682310

申请日：2015-04-09

Applicant: ARM Limited

Inventor： Hakan Persson ,  Matt Evans ,  Jason Parker ,  Marc Zyngier

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: A data processing system comprises one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. The system also comprises an accelerator that provides a shared resource for a plurality of the applications, an input/output module comprising one or more input/output interfaces for the submission of tasks to the accelerator, a hypervisor that manages the allocation of the input/output interfaces to the one or more operating systems and a storage area accessible by the hypervisor and the accelerator. The accelerator is capable of writing one or more selected pieces of information representative of one or more scheduling statistics of the accelerator periodically to the storage area without having received a request for the one or more selected pieces of information from the hypervisor.

公开(公告)号：US20140372722A1

公开(公告)日：2014-12-18

申请号：US13916722

申请日：2013-06-13

Applicant: ARM Limited

Inventor： Oskar Flordal ,  Hakan Persson ,  Andreas Engh-Halstvedt

IPC: G06F12/02

CPC classification number: G06F12/02 ,  G06F9/5016 ,  G06F12/0284 ,  G06T1/60

Abstract: A processing system comprises plural processing cores and a task allocator for allocating tasks to the processing cores. The processing cores perform the tasks that are allocated to them so as to produce results for the tasks, the results being stored by the processing cores in a buffer. The task allocator indicates to the processing cores memory portions within the buffer in which to store the results. When the processing cores determine that a given memory portion is becoming full, the processing cores request that the task allocator indicates a new memory portion in which to store its results. The processing system allows the task allocator to dynamically and efficiently allocate memory portions to plural processing cores without the task allocator 40 needing to know the sizes of the results being produced by the processing cores.

Abstract translation: 处理系统包括多个处理核和用于将任务分配给处理核的任务分配器。 处理核心执行分配给它们的任务，以产生任务的结果，结果由处理核心存储在缓冲区中。 任务分配器向处理核心指示缓冲器内存储结果的内存部分。 当处理核心确定给定的存储器部分变满时，处理核心请求任务分配器指示在其中存储其结果的新的存储器部分。 处理系统允许任务分配器动态且有效地将存储器部分分配给多个处理核，而任务分配器40需要知道由处理核产生的结果的大小。

公开(公告)号：US10250709B2

公开(公告)日：2019-04-02

申请号：US15099244

申请日：2016-04-14

Applicant: ARM Limited

Inventor： Jesus Javier de los Reyes Darias ,  Hakan Persson ,  Roko Grubisic ,  Vinod Pisharath Hari Pai

IPC: H04L12/18 ,  H04L12/54 ,  H04L29/06 ,  H04L29/08 ,  H04L12/861 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0891

Abstract: A data processing apparatus has multiple caches and a controller for controlling the caches. The controller and caches communicate over a first network and a second network. The first network is used for unicast communication from the controller to a specific one of the caches. The second network is used for communication of a multicast communication from the controller to two or more of the caches.

公开(公告)号：US09798565B2

公开(公告)日：2017-10-24

申请号：US14682313

申请日：2015-04-09

Applicant: ARM Limited

Inventor： Hakan Persson ,  Matt Evans ,  Jason Parker ,  Marc Zyngier

IPC: G06F9/455 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/50 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: A data processing system includes one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. An accelerator provides a shared resource for a plurality of the applications and has one or more input/output interfaces for the submission of tasks to the accelerator from an application. A hypervisor manages the allocation of the input/output interfaces to the one or more operating systems and a hypervisor interface enables communication between the hypervisor and the accelerator. The system is capable of being configured such that an operating system that has been allocated an input/output interface is capable of communicating with the accelerator via the input/output interface independently of the hypervisor. A memory management unit is capable of providing an isolated region of a memory for use by the operating system while the operating system retains its allocated input/output interface.

公开(公告)号：US20160260249A1

公开(公告)日：2016-09-08

申请号：US14639346

申请日：2015-03-05

Applicant: ARM Limited

Inventor： Hakan Persson ,  David Shreiner

IPC: G06T17/10 ,  G06K9/62 ,  G06T7/00 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06T17/10 ,  G06K9/6267 ,  G06T1/20 ,  G06T1/60 ,  G06T7/50 ,  G06T11/40 ,  G06T15/005

Abstract: An apparatus for processing primitives in a tile-based graphics processing system includes processing circuitry which is configured to determine, for a group of plural primitives, the rendering tiles that the group of primitives should be processed for. The processing circuitry is also configured to store, for the group of primitives, a data entry containing an indication of the identity of the plurality of primitives in the group of primitives, and an indication of the rendering tiles that it has been determined the group of primitives should be processed for.

Abstract translation: 一种用于在基于瓦片的图形处理系统中处理图元的装置包括处理电路，其被配置为针对一组多个图元确定应该对该图元组进行处理的渲染图块。 所述处理电路还被配置为存储对于所述原语组的数据条目，所述数据条目包含所述图元组中的所述多个图元的标识的指示，以及所述渲染图块的指示， 应处理原语。

公开(公告)号：US20150293776A1

公开(公告)日：2015-10-15

申请号：US14682313

申请日：2015-04-09

Applicant: ARM Limited

Inventor： Hakan Persson ,  Matt Evans ,  Jason Parker ,  Marc Zyngier

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/50 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: A data processing system includes one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. An accelerator provides a shared resource for a plurality of the applications and has one or more input/output interfaces for the submission of tasks to the accelerator from an application. A hypervisor manages the allocation of the input/output interfaces to the one or more operating systems and a hypervisor interface enables communication between the hypervisor and the accelerator. The system is capable of being configured such that an operating system that has been allocated an input/output interface is capable of communicating with the accelerator via the input/output interface independently of the hypervisor. A memory management unit is capable of providing an isolated region of a memory for use by the operating system whilst the operating system retains its allocated input/output interface.

Abstract translation: 数据处理系统包括一个或多个处理器，每个处理器执行一个或多个操作系统。 每个操作系统包括一个或多个应用程序。 加速器为多个应用提供共享资源，并具有用于从应用程序向加速器提交任务的一个或多个输入/输出接口。 虚拟机管理程序管理对一个或多个操作系统的输入/输出接口的分配，管理程序接口实现管理程序和加速器之间的通信。 该系统能够被配置为使得已经被分配了输入/输出接口的操作系统能够经由独立于管理程序的输入/输出接口与加速器通信。 存储器管理单元能够提供存储器的隔离区域，以供操作系统使用，同时操作系统保留其分配的输入/输出接口。