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公开(公告)号：US11966739B2
公开(公告)日：2024-04-23
申请号：US17941387
申请日：2022-09-09
Applicant: Arm Limited
Inventor： Matthew James Walker , Mbou Eyole , Giacomo Gabrielli , Balaji Venu
CPC classification number: G06F9/30123 , G06F9/30138 , G06F9/3824 , G06F9/4881 , G06F9/30098 , G06F9/30145
Abstract: There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.
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公开(公告)号：US20230289405A1
公开(公告)日：2023-09-14
申请号：US18016916
申请日：2021-07-19
Applicant: Arm Limited
Inventor： Mbou Eyole , Balaji Venu
IPC: G06F18/2415 , G06F17/11
CPC classification number: G06F18/2415 , G06F17/11
Abstract: An entropy calculation for certainty-based classification networks is provided. An integer operand p is received. A remainder portion of the integer operand p is determined based on a range reduction operation. A scaled integer operand is determined based on the integer operand p. An index for a data structure, such as, for example, a look-up table (LUT), is determined based on the remainder portion of the integer operand p and a parameter N associated with the data structure. A data structure value in the data structure is looked up based on the index. A scaled entropy value is generated by adding the data structure value to the scaled integer operand. An entropy value is determined based on the scaled entropy value, and the entropy value is output.
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公开(公告)号：US11263073B2
公开(公告)日：2022-03-01
申请号：US16641377
申请日：2018-08-30
Applicant: ARM Limited
Inventor： Matthias Lothar Boettcher , Mbou Eyole , Balaji Venu
Abstract: An apparatus has a processing pipeline (2) comprising an execute stage (30) and at least one front end stage (10), (20), (25) for controlling which micro operations are issued to the execute stage. The pipeline has an intra-core lockstep mode of operation in which the at least one front end stage (10), (20), (25) issues micro operations for controlling the execute stage (30) to perform main processing and checker processing. The checker processing comprises redundant operations corresponding to associated main operations of at least part of the main processing. Error handling circuitry (200), (210) is responsive to the detection of a mismatch between information associated with given checker and main operations to trigger a recovery operation to correct an error and continue forward progress of the main processing.
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公开(公告)号：US10108486B2
公开(公告)日：2018-10-23
申请号：US14850992
申请日：2015-09-11
Applicant: ARM LIMITED
Inventor： Emre Özer , Balaji Venu
IPC: G06F11/10
Abstract: A state indicating value is encoded with a one-hot or one-cold encoding and each bit of the state indicating value is stored in a different portion of a storage element. Parity values are determined for each portion of the storage element and stored to a parity storage element. This allows errors caused by single event upsets or multi-bit upsets to be detected and corrected, with lower hardware cost compared to alternative approaches.
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公开(公告)号：US20230289654A1
公开(公告)日：2023-09-14
申请号：US18016914
申请日：2021-07-19
Applicant: Arm Limited
Inventor： Balaji Venu , Mbou Eyole
Abstract: A certainty-based prediction apparatus and method are provided. A plurality of main classifier (MC) modules each predict an MC predicted class based on input data, and determine an MC certainty. Each MC module processes a pre-trained, machine learning main classifier having at least one expert class and a plurality of non-expert classes. An expert classifier (EC) module associated with each expert class predicts an EC predicted class based on the input data. Each EC module processes a pre-trained, machine learning expert classifier having two classes including an associated expert class and a residual class that includes any non-associated expert classes and the plurality of non-expert classes. A final predicted class decision module determines a final predicted class and a final certainty based on each MC predicted class, each MC certainty and each EC predicted class. The final predicted class and the final certainty are output.
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Patent Agency Ranking
公开(公告)号：US11494256B2
公开(公告)日：2022-11-08
申请号：US17261217
申请日：2019-06-06
Applicant: Arm Limited
Inventor： Milosch Meriac , Emre Özer , Xabier Iturbe , Balaji Venu , Shidhartha Das
Abstract: An apparatus comprises a plurality of redundant processing units to perform data processing redundantly in lockstep; common mode fault detection circuitry to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory shared between the plurality of redundant processing units; and memory checking circuitry to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry indicating that the event indicative of a potential common mode fault has been detected.
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公开(公告)号：US11113164B2
公开(公告)日：2021-09-07
申请号：US16641387
申请日：2018-08-30
Applicant: ARM Limited
Inventor： Balaji Venu , Matthias Lothar Boettcher , Mbou Eyole
Abstract: A buffer (72), (74), (76), (60), (78), (20), (82-90) has a number of entries for buffering items associated with data processing operations. Buffer control circuitry (100) has a redundant allocation mode in which, on allocating a given item to the buffer, the item is allocated to two or more redundant entries of the buffer. On reading or draining an item from the buffer, the redundant entries are compared and an error handling response is triggered if a mismatch is detected. By effectively reducing the buffer capacity, this simplifies testing for faults in buffer entries.
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公开(公告)号：US10810094B2
公开(公告)日：2020-10-20
申请号：US16014154
申请日：2018-06-21
Applicant: Arm Limited
Inventor： Milosch Meriac , Xabier Iturbe , Emre Ozer , Balaji Venu , Shidhartha Das
Abstract: Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.
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公开(公告)号：US10523186B1
公开(公告)日：2019-12-31
申请号：US16206234
申请日：2018-11-30
Applicant: Arm Limited
Inventor： Balaji Venu , Reiley Jeyapaul , Xabier Iturbe , Matthew James Horsnell , David Michael Gilday
IPC: G06F17/50 , G06F9/455 , H03K3/037 , G01R31/3183
Abstract: An apparatus is provided comprising receiving circuitry to receive a representation of a circuit comprising a plurality of flops. Categorisation circuitry determines data dependencies between the flops from the representation and generates a categorisation of the flops into one of at least: a vulnerable category, a conditional category, and an isolated category, in dependence on the data dependencies. The categorisation indicates the vulnerability of the flops to transient errors. Output circuitry outputs the categorisation of the flops. The conditional category comprises those of the flops whose change in value is indicated by a change in a value in a corresponding flop in the flops or corresponding signal. The vulnerable category comprises those of the flops that are absent from the conditional category and whose change in value is affected by one of the flops or a signal and the isolated category comprises the flops that are absent from the conditional category and that are absent from the vulnerable category.
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公开(公告)号：US10185635B2
公开(公告)日：2019-01-22
申请号：US15463066
申请日：2017-03-20
Applicant: ARM Limited
Inventor： Balaji Venu , Xabier Iturbe , Emre Özer
Abstract: An apparatus comprises at least three processing circuits to perform redundant processing of common program instructions. Error detection circuitry coupled to a plurality of signal nodes of each of said at least three processing circuits comprises comparison circuitry to detect a mismatch between signals on corresponding signal nodes in said at least three processing circuits, the plurality of signal nodes forming a first group of signal nodes and a second group of signal nodes. In response to the mismatch being detected in relation to corresponding signal nodes within the first group, the error detection circuitry is configured to generate a first trigger for a full recovery process for resolving an error detected for an erroneous processing circuit using state information derived from at least two other processing circuits. In response to the mismatch being detected in relation to corresponding signal nodes within the second group the error detection circuitry is configured to generate a second trigger for a targeted recovery process for a subset of components of the erroneous processing circuit. By implementing a targeted recovery process for a subset of components of an erroneous processing circuit a cheaper recovery process may be provided.
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