公开(公告)号：US11005461B2

公开(公告)日：2021-05-11

申请号：US16004009

申请日：2018-06-08

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sai Sriharsha Manapragada ,  Yicong Li ,  Yew Keong Chong ,  Bikas Maiti ,  Sanjay Mangal ,  Hsin-Yu Chen

IPC: H03K3/356 ,  H03K17/22

Abstract: Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.

公开(公告)号：US10854280B2

公开(公告)日：2020-12-01

申请号：US15691001

申请日：2017-08-30

Applicant: ARM Limited

Inventor： Abhairaj Singh ,  Vivek Asthana ,  Monu Rathore ,  Ankur Goel ,  Nikhil Kaushik ,  Rachit Ahuja ,  Rahul Mathur ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C11/408 ,  G11C11/419 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.