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    Memory device and method of performing access operations within such a memory device
    2.
    发明授权
    Memory device and method of performing access operations within such a memory device 有权
    在这种存储装置内执行存取操作的存储装置和方法

    公开(公告)号：US09064559B2

    公开(公告)日：2015-06-23

    申请号：US13967879

    申请日：2013-08-15

    Applicant: ARM LIMITED

    Inventor： Bikas Maiti ,  Yew Keong Chong ,  Martin Jay Kinkade

    IPC: G11C7/22

    CPC classification number: G11C7/22 ,  G11C5/148 ,  G11C7/227 ,  G11C11/419

    Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, a plurality of word lines, each word line being coupled to an associated row of memory cells, and a plurality of bit lines, each bit line being coupled to an associated column of memory cells. Access circuitry is coupled to the word lines and the bit lines in order to perform access operations in respect of selected memory cells within the array. Control circuitry controls operation of the access circuitry and includes self-timed path (STP) delay circuitry. The control circuitry employs the delay indication when controlling the access circuitry to perform said access operations. Voltage supply control circuitry switches the voltage supply to at least one portion of the STP delay circuitry between a peripheral voltage supply and an array voltage supply dependent on a control signal.

    Abstract translation: 存储器件包括布置成多个行和列的存储器单元的阵列，多个字线，每个字线耦合到相关行的存储器单元，以及多个位线，每个位线耦合到 相关的存储单元列。 访问电路被耦合到字线和位线，以便对阵列内的所选存储单元执行访问操作。 控制电路控制接入电路的操作，并且包括自定时路径（STP）延迟电路。 控制电路在控制访问电路执行所述访问操作时采用延迟指示。 电压供应控制电路根据控制信号将外部电压源和阵列电压电源之间的电压供应切换到STP延迟电路的至少一部分。

    Contention-adapted read-write pulse generation circuitry
    3.
    发明授权
    Contention-adapted read-write pulse generation circuitry 有权

    公开(公告)号：US11501809B1

    公开(公告)日：2022-11-15

    申请号：US17348209

    申请日：2021-06-15

    Applicant: Arm Limited

    Inventor： Sanjay Mangal ,  Bikas Maiti

    IPC: G11C8/14 ,  G11C8/08 ,  G11C7/12 ,  G06F13/16 ,  G11C7/18 ,  G11C7/10

    Abstract: Various implementations described herein refer to a device having an address bus that provides multi-port addresses from multiple ports including a first address from a first port and a second address from a second port. The device may have column contention-detection circuitry that receives the multi-port addresses from the address bus, compares the first address from the first port with the second address from the second port and provides a contention adjustment signal based on the comparison between the first address and the second address. The device may have bitline collision circuitry that receives the contention adjustment signal, senses wire-to-wire variation related to bitline coupling effects and provides a bitline collision signal based on sensing the bitline coupling effects.

    Clock generation circuitry for memory applications
    4.
    发明授权
    Clock generation circuitry for memory applications 有权

    公开(公告)号：US10008260B1

    公开(公告)日：2018-06-26

    申请号：US15490352

    申请日：2017-04-18

    Applicant: ARM Limited

    Inventor： Bikas Maiti ,  Rahul Mathur ,  Sanjay Mangal

    IPC: G11C7/22 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/22 ,  G11C7/222

    Abstract: Various implementations described herein are directed to an integrated circuit having level shift circuitry that receives a clock signal in a first voltage domain from a first voltage supply and provides a level shifted clock signal in a second voltage domain based on a second voltage supply that is different than the first voltage supply. The integrated circuit may include clock generator pulse circuitry that receives the clock signal in the first voltage domain from the first voltage supply and receives the level shifted clock signal in the second voltage domain from the level shift circuitry.

    Write assist circuitry
    5.
    发明授权
    Write assist circuitry 有权

    公开(公告)号：US09997217B1

    公开(公告)日：2018-06-12

    申请号：US15477516

    申请日：2017-04-03

    Applicant: ARM Limited

    Inventor： Ankur Goel ,  Munish Kumar ,  Nitin Jindal ,  Rahul Mathur ,  Shruti Aggarwal ,  Bikas Maiti ,  Yew Keong Chong

    IPC: G11C7/10 ,  G11C7/12 ,  G11C8/16 ,  G11C8/18 ,  G11C7/20

    CPC classification number: G11C7/12 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/419

    Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.

    Column Redundancy Techniques
    6.
    发明申请
    Column Redundancy Techniques 有权

    公开(公告)号：US20230016339A1

    公开(公告)日：2023-01-19

    申请号：US17375887

    申请日：2021-07-14

    Applicant: Arm Limited

    Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Bikas Maiti ,  Vivek Nautiyal

    IPC: G11C29/00 ,  G11C29/18 ,  G11C7/10

    Abstract: Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.

    Column redundancy techniques
    9.
    发明授权
    Column redundancy techniques 有权

    公开(公告)号：US11664086B2

    公开(公告)日：2023-05-30

    申请号：US17375887

    申请日：2021-07-14

    Applicant: Arm Limited

    Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Bikas Maiti ,  Vivek Nautiyal

    IPC: G11C29/00 ,  G11C7/10 ,  G11C29/18

    CPC classification number: G11C29/76 ,  G11C7/1012 ,  G11C29/18 ,  G11C29/785 ,  G11C2029/1802

    Abstract: Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.

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