公开(公告)号：US20250078912A1

公开(公告)日：2025-03-06

申请号：US18240875

申请日：2023-08-31

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Rahul Mathur

IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

Abstract: Various implementations described herein are directed to a device having first transistors arranged as cross-coupled inverters coupled between a disconnect node and ground. The device may have second transistors arranged as passgates coupled between the cross-coupled inverters and bitlines. The device may have third transistors coupled between a voltage supply and the disconnect node.

公开(公告)号：US20240290363A1

公开(公告)日：2024-08-29

申请号：US18113438

申请日：2023-02-23

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Sanjay Mangal ,  Hemavathi Chaya ,  Kyung Woo Kim ,  Pratik Ghanshambhai Satasia ,  Edward Martin McCombs

IPC: G11C7/22 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C7/222 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device with a first clock generator that provides a first pulse signal based on a clock signal, wherein the first clock generator has a first tracking circuit that provides a first reset signal based on the first pulse signal. The device may include a second clock generator that provides a second pulse signal based on the clock signal, wherein the second clock generator has a second tracking circuit that provides a first control signal based on the second pulse signal. Also, the device may include a third clock generator that provides a third pulse signal based on the first reset signal, wherein the third clock generator has a logic circuit that provides a second control signal based on the third pulse signal.

公开(公告)号：US20220343970A1

公开(公告)日：2022-10-27

申请号：US17238683

申请日：2021-04-23

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Andy Wangkun Chen

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C5/06

Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.

公开(公告)号：US20180342271A1

公开(公告)日：2018-11-29

申请号：US15603252

申请日：2017-05-23

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Rahul Mathur ,  Abhishek Baradia ,  Hsin-Yu Chen

IPC: G11C7/12 ,  G11C7/22

CPC classification number: G11C8/10 ,  G11C8/06

Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.

公开(公告)号：US20240055047A1

公开(公告)日：2024-02-15

申请号：US17885709

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Edward Martin McCombs, JR. ,  Andrew David Tune ,  Sean James Salisbury ,  Rahul Mathur ,  Hsin-Yu Chen ,  Phani Raja Bhushan Chalasani

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091

Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

公开(公告)号：US20220246206A1

公开(公告)日：2022-08-04

申请号：US17162532

申请日：2021-01-29

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Rahul Mathur ,  Andy Wangkun Chen

IPC: G11C11/419 ,  G11C11/418

Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.

公开(公告)号：US10008260B1

公开(公告)日：2018-06-26

申请号：US15490352

申请日：2017-04-18

Applicant: ARM Limited

Inventor： Bikas Maiti ,  Rahul Mathur ,  Sanjay Mangal

IPC: G11C7/22 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/22 ,  G11C7/222

Abstract: Various implementations described herein are directed to an integrated circuit having level shift circuitry that receives a clock signal in a first voltage domain from a first voltage supply and provides a level shifted clock signal in a second voltage domain based on a second voltage supply that is different than the first voltage supply. The integrated circuit may include clock generator pulse circuitry that receives the clock signal in the first voltage domain from the first voltage supply and receives the level shifted clock signal in the second voltage domain from the level shift circuitry.

公开(公告)号：US09997217B1

公开(公告)日：2018-06-12

申请号：US15477516

申请日：2017-04-03

Applicant: ARM Limited

Inventor： Ankur Goel ,  Munish Kumar ,  Nitin Jindal ,  Rahul Mathur ,  Shruti Aggarwal ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/16 ,  G11C8/18 ,  G11C7/20

CPC classification number: G11C7/12 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.

公开(公告)号：US09620200B1

公开(公告)日：2017-04-11

申请号：US15081869

申请日：2016-03-26

Applicant: ARM Limited

Inventor： Sanjay Mangal ,  Gus Yeung ,  Martin Jay Kinkade ,  Rahul Mathur ,  Bal S. Sandhu ,  George McNeil Lattimore

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/413 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  H01L27/11 ,  H01L27/1104

Abstract: Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

公开(公告)号：US20250087251A1

公开(公告)日：2025-03-13

申请号：US18367902

申请日：2023-09-13

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Andy Wangkun Chen

IPC: G11C5/14

Abstract: Various implementations described herein are directed to a device having a power-gate structure with multiple transistors including a first transistor and a second transistor. The first transistor may be coupled between a first voltage node and a second voltage node, and the second transistor may be coupled between the second voltage node and a third voltage node that is coupled to the second voltage node.