公开(公告)号：US20170076032A1

公开(公告)日：2017-03-16

申请号：US14851644

申请日：2015-09-11

Applicant: ARM Limited

Inventor： Gregory Munson Yeric

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/12 ,  G06F2217/78 ,  G06F2217/84 ,  Y02P90/265

Abstract: Various implementations described herein are directed to systems and methods for mitigating contact resistance. In one implementation, a method may include analyzing operating conditions for cells of an integrated circuit. The method may include selectively marking instances of the cells having timing degradation along a critical path of the integrated circuit. The method may include reducing contact resistance for the selectively marked instances of the cells having timing degradation.

Abstract translation: 本文描述的各种实现涉及用于减轻接触电阻的系统和方法。 在一个实现中，方法可以包括分析集成电路的单元的操作条件。 该方法可以包括沿着集成电路的关键路径选择性地标记具有定时劣化的小区的实例。 该方法可以包括降低具有定时劣化的小区的选择性标记的实例的接触电阻。

公开(公告)号：US20210389520A1

公开(公告)日：2021-12-16

申请号：US17288498

申请日：2019-10-23

Applicant: Arm Limited

Inventor： Vinay Vashishtha ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha ,  Gregory Munson Yeric

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/42

Abstract: Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.

公开(公告)号：US10937831B2

公开(公告)日：2021-03-02

申请号：US16600372

申请日：2019-10-11

Applicant: Arm Limited

Inventor： Lucian Shifren ,  Kimberly Gay Reid ,  Gregory Munson Yeric

IPC: H01L27/24 ,  H01L45/00

Abstract: Subject matter disclosed herein may relate to devices formed from correlated electron material.

公开(公告)号：US10707415B2

公开(公告)日：2020-07-07

申请号：US16200214

申请日：2018-11-26

Applicant: Arm Limited

Inventor： Lucian Shifren ,  Kimberly Gay Reid ,  Gregory Munson Yeric ,  Manuj Rathor ,  Glen Arnold Rosendale

IPC: H01L45/00 ,  H01L27/24 ,  H01L25/00

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters. In embodiments, CEM devices fabricated at a first stage of a wafer fabrication process, such as a front-end-of-line stage, may differ from CEM devices fabricated at a second stage of a wafer fabrication process, such as a middle-of-line stage or a back-end-of-line stage, for example.

公开(公告)号：US20190173008A1

公开(公告)日：2019-06-06

申请号：US16200214

申请日：2018-11-26

Applicant: Arm Limited

Inventor： Lucian Shifren ,  Kimberly Gay Reid ,  Gregory Munson Yeric ,  Manuj Rathor ,  Glen Arnold Rosendale

IPC: H01L45/00 ,  H01L27/24 ,  H01L25/00

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters. In embodiments, CEM devices fabricated at a first stage of a wafer fabrication process, such as a front-end-of-line stage, may differ from CEM devices fabricated at a second stage of a wafer fabrication process, such as a middle-of-line stage or a back-end-of-line stage, for example.