公开(公告)号：US20180018420A1

公开(公告)日：2018-01-18

申请号：US15210109

申请日：2016-07-14

Applicant: ARM Limited

Inventor： Brian Tracy Cline ,  Gregory Munson Yeric

IPC: G06F17/50 ,  H01L21/768 ,  H01L23/528

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G03F7/2022 ,  G06F17/5045 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00 ,  H01L21/76892 ,  H01L23/528

Abstract: A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout data file to further include mask information having at least a first set of trim features associated with one or more redundant metal portions and one or more active metal portions of the layout data file. The method also comprises determining the one or more redundant metal portions to be perforated. The method further comprises modifying the mask information to further include a second set of trim features for perforating the one or more redundant metal portions. The first set of trim features and the second set of trim features are associated with a trim mask of the SAMP process.

公开(公告)号：US09875332B2

公开(公告)日：2018-01-23

申请号：US14851644

申请日：2015-09-11

Applicant: ARM Limited

Inventor： Gregory Munson Yeric

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/12 ,  G06F2217/78 ,  G06F2217/84 ,  Y02P90/265

Abstract: Various implementations described herein are directed to systems and methods for mitigating contact resistance. In one implementation, a method may include analyzing operating conditions for cells of an integrated circuit. The method may include selectively marking instances of the cells having timing degradation along a critical path of the integrated circuit. The method may include reducing contact resistance for the selectively marked instances of the cells having timing degradation.

公开(公告)号：US20170365600A1

公开(公告)日：2017-12-21

申请号：US15188544

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar Sinha ,  Robert Campbell Aitken ,  Brian Tracy Cline ,  Gregory Munson Yeric ,  Kyungwook Chang

IPC: H01L27/06 ,  H01L23/528 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/73207

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.

公开(公告)号：US20200052201A1

公开(公告)日：2020-02-13

申请号：US16659206

申请日：2019-10-21

Applicant: Arm Limited

Inventor： Lucian Shifren ,  Kimberly Gay Reid ,  Gregory Munson Yeric

IPC: H01L45/00

Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) device. In embodiments, after formation of the one or more CEM traces, a spacer may be deposited in contact with the one or more CEM traces. The spacer may operate to control an atomic concentration of dopant within the one or more CEM traces by replenishing dopant that may be lost during subsequent processing and/or by forming a seal to reduce further loss of dopant from the one or more CEM traces.

公开(公告)号：US20200043982A1

公开(公告)日：2020-02-06

申请号：US16600372

申请日：2019-10-11

Applicant: Arm Limited

Inventor： Lucian Shifren ,  Kimberly Gay Reid ,  Gregory Munson Yeric

IPC: H01L27/24 ,  H01L45/00

Abstract: Subject matter disclosed herein may relate to devices formed from correlated electron material.

公开(公告)号：US10036774B2

公开(公告)日：2018-07-31

申请号：US14560755

申请日：2014-12-04

Applicant: ARM Limited

Inventor： Gregory Munson Yeric ,  Vikas Chandra

IPC: G01R31/00 ,  G01R31/28 ,  H01L21/66 ,  H01L25/065

CPC classification number: G01R31/2855 ,  G01R31/2856 ,  H01L22/30 ,  H01L22/34 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73204 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.

公开(公告)号：US10002222B2

公开(公告)日：2018-06-19

申请号：US15210109

申请日：2016-07-14

Applicant: ARM Limited

Inventor： Brian Tracy Cline ,  Gregory Munson Yeric

IPC: G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  G03F1/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G03F7/2022 ,  G06F17/5045 ,  G06F17/5077 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00 ,  H01L21/76892 ,  H01L23/522 ,  H01L23/528

Abstract: A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout data file to further include mask information having at least a first set of trim features associated with one or more redundant metal portions and one or more active metal portions of the layout data file. The method also comprises determining the one or more redundant metal portions to be perforated. The method further comprises modifying the mask information to further include a second set of trim features for perforating the one or more redundant metal portions. The first set of trim features and the second set of trim features are associated with a trim mask of the SAMP process.

公开(公告)号：US09672316B2

公开(公告)日：2017-06-06

申请号：US13944129

申请日：2013-07-17

Applicant: ARM LIMITED

Inventor： Gregory Munson Yeric

IPC: G06F17/50 ,  H01L21/027 ,  G03F7/20 ,  H01L21/66

CPC classification number: G06F17/5081 ,  G03F7/70383 ,  G03F7/70433 ,  G06F2217/12 ,  H01L21/027 ,  H01L22/14 ,  H01L22/20

Abstract: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step is varied in dependence upon those performance characteristics. Accordingly, the performance of an individual integrated circuit, wafer of integrated circuits or batch of wafers may be altered.

公开(公告)号：US10303840B2

公开(公告)日：2019-05-28

申请号：US15498804

申请日：2017-04-27

Applicant: ARM Limited

Inventor： Gregory Munson Yeric

IPC: G03F7/20 ,  G06F17/50 ,  H01L21/66 ,  H01L21/027

Abstract: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step is varied in dependence upon those performance characteristics. Accordingly, the performance of an individual integrated circuit, wafer of integrated circuits or batch of wafers may be altered.

公开(公告)号：US09929149B2

公开(公告)日：2018-03-27

申请号：US15188544

申请日：2016-06-21

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar Sinha ,  Robert Campbell Aitken ,  Brian Tracy Cline ,  Gregory Munson Yeric ,  Kyungwook Chang

IPC: H01L27/06 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/73207

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.