公开(公告)号：US20230118268A1

公开(公告)日：2023-04-20

申请号：US17501257

申请日：2021-10-14

Applicant: Arm Limited

Inventor： Guillaume BOLBENES ,  Florent BEGON ,  Thibaut Elie LANOIS ,  Houdhaifa BOUZGUARROU

IPC: G06F9/38 ,  G06F9/30

Abstract: Aspects of the present disclosure relate to an apparatus comprising prediction circuitry having a plurality of hierarchical prediction units to perform respective hierarchical predictions of instructions for execution, wherein predictions higher in the hierarchy have a higher expected accuracy than predictions lower in the hierarchy. Responsive to a given prediction higher in the hierarchy being different to a corresponding prediction lower in the hierarchy, the corresponding prediction lower in the hierarchy is corrected. A prediction correction metric determination unit determines a prediction correction metric indicative of an incidence of uncorrected predictions performed by the prediction circuitry. Fetch circuitry fetches instructions predicted by at least one of said plurality of hierarchical predictions, and delays said fetching based on the prediction correction metric indicating an incidence of uncorrected predictions below a threshold.

公开(公告)号：US20220261252A1

公开(公告)日：2022-08-18

申请号：US17175150

申请日：2021-02-12

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Thibaut Elie LANOIS

IPC: G06F9/38 ,  G06F9/30

Abstract: Circuitry comprises prediction storage to store, for a given branch operation, a multi-bit data item and indicator data defining a subset of bits of the multi-bit data item, the subset being one of an ordered succession of different subsets of bits of the multi-bit data item; and prediction generator circuitry to generate a predicted branch outcome for the given branch operation in dependence upon the subset of bits defined by the indicator data and, in response to generation of the predicted branch outcome, to change the subset of bits defined by the indicator data to a next subset in the ordered succession of subsets.

公开(公告)号：US20200285476A1

公开(公告)日：2020-09-10

申请号：US16292454

申请日：2019-03-05

Applicant: Arm Limited

Inventor： Guillaume BOLBENES ,  Albin Pierrick TONNERRE ,  Houdhaifa BOUZGUARROU

IPC: G06F9/38 ,  G06N5/02 ,  G06F9/30

Abstract: An apparatus and method are provided for handling prediction information. The apparatus has processing circuitry for performing data processing operations in response to instructions, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction comprising a sequence of instructions. Prediction circuitry is used to generate predictions in relation to instruction flow changing instructions, and prediction storage is provided to store a plurality of items of prediction information that are referenced by the prediction circuitry when generating the predictions. The items of prediction information maintained by the prediction storage change based on the instructions being executed by the processing circuitry. A recovery storage is activated by the transactional memory support circuitry at a transaction start point to store a restore pointer identifying a chosen location in the prediction storage. Between the transaction start point and the transaction end point, the recovery storage receives any item of prediction information removed from the prediction storage that was present in the prediction storage at the transaction start point. In response to the transaction being aborted, the restore pointer is used in order to discard from the prediction storage any items of prediction information added to the prediction storage after the transaction start point, and in addition any items of prediction information stored in the recovery storage are stored back into the prediction storage. This can significantly improve prediction accuracy in systems that may need to retry transactions due to a transaction abort, without requiring the entire prediction storage state to be captured at the transaction start point.

公开(公告)号：US20200057643A1

公开(公告)日：2020-02-20

申请号：US16105028

申请日：2018-08-20

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Vincenzo CONSALES

IPC: G06F9/38

Abstract: An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry for executing instructions out-of-order with respect to original program order, and event counting prediction circuitry for maintaining event count values for branch instructions, for use in making branch outcome predictions for those branch instructions. Further, checkpointing storage stores state information of the apparatus at a plurality of checkpoints to enable the state information to be restored for a determined one of those checkpoints in response to a flush event. The event counting prediction circuitry has training storage with a first number of training entries, each training entry being associated with a branch instruction. The event counting prediction circuitry implements a training phase for each training entry during which it seeks to determine an event count value for the associated branch instruction based on branch outcome behaviour of the branch instruction observed for instances of execution of the branch instruction that have been committed by the processing circuitry. The event counting prediction circuitry further has access storage with a second number of active entries, where the second number is less than the first number. Each active entry is associated with a branch instruction for which an event count value has been successfully determined during the training phase. The event counting prediction circuitry is arranged to make branch outcome predictions for branch instructions having an active entry. At each checkpoint, state information for the active entries is stored to the checkpointing storage. This provides a particularly efficient form of event counting prediction circuitry that can be used in out-of-order systems, while reducing the amount of state information that needs to stored into the checkpointing storage at each checkpoint.

公开(公告)号：US20190138315A1

公开(公告)日：2019-05-09

申请号：US15806605

申请日：2017-11-08

Applicant: Arm Limited

Inventor： Guillaume BOLBENES ,  Houdhaifa BOUZGUARROU ,  Luc ORION ,  Eddy LAPEYRE

IPC: G06F9/38 ,  G06F9/30

Abstract: Program flow prediction circuitry comprises a history register to store history data for at least one or more most recently executed branch instructions; a memory to store a plurality of sets of weight values, one set for each of a group of portions of one or more bits of the history data; access circuitry to access, for a current branch instruction to be predicted, a weight value for each of the portions of one or more bits of the history data by selecting from the set of weight values in dependence upon a current value of the portions of the history data; a combiner to generate a combined weight value by combining the weight values accessed by the access circuitry; a comparator to compare the combined weight value with a prediction threshold value to detect whether or not a branch represented by the current branch instruction is predicted to be taken; and weight modifier circuitry to modify the accessed weight values in dependence upon a resolution of whether the branch represented by the current branch instruction is taken or not.

公开(公告)号：US20250085971A1

公开(公告)日：2025-03-13

申请号：US18462742

申请日：2023-09-07

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Alexander Cole SHULYAK ,  Rami Mohammad AL SHEIKH

IPC: G06F9/32 ,  G06F9/30

Abstract: A data processing apparatus includes pointer storage configured to store pointer values for pointers. Increment circuitry, responsive to one or more increment events, increments each of the pointer values in dependence on a corresponding live pointer value update condition from corresponding live pointer value update conditions. The corresponding live pointer value update condition is different for each of the pointers. History storage circuitry stores resolved behaviours of instances of a control flow instruction, each of the resolved behaviours being associated with one of the pointers. At least one of the live pointer value update conditions is changeable at runtime. Consequently, storage can be reduced as compared to a situation where all pointer value update conditions are active.

公开(公告)号：US20250068426A1

公开(公告)日：2025-02-27

申请号：US18454165

申请日：2023-08-23

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Alexander Cole SHULYAK

IPC: G06F9/38 ,  G06F12/0802

Abstract: An apparatus stores pointer values for pointers which are incremented differentially and has prediction circuitry to maintain prediction entries each identifying a control flow instruction, an associated pointer, and a behaviour record indicating resolved behaviour of the control flow instruction. Resolved behaviour stored in a selected element of the behaviour record identified using a pointer value of the associated pointer may be used as predicted behaviour for a control flow instruction. The prediction entries include a first type of prediction entry and a further type of prediction entry, where prediction circuitry uses each prediction entry of the first type to identify a control flow instruction whose associated pointer is within a first subset of the pointers, and uses each prediction entry of a further type to identify a control flow instruction whose associated pointer is within a further subset of the pointers excluding at least one pointer of the first subset.

公开(公告)号：US20240370266A1

公开(公告)日：2024-11-07

申请号：US18312052

申请日：2023-05-04

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Yasuo ISHII ,  Dam SUNWOO ,  Houdhaifa BOUZGUARROU

IPC: G06F9/38 ,  G06F12/0875

Abstract: An apparatus is provided having pointer storage to store pointer values for a plurality of pointers, with the pointer values of the pointers being differentially incremented in response to a series of increment events. Tracker circuitry maintains a plurality of tracker entries, each tracker entry identifying a control flow instruction and a current active pointer (from amongst the pointers) to be associated with that control flow instruction. Cache circuitry maintains a plurality of cache entries, each cache entry storing a resolved behaviour of an instance of a control flow instruction identified by a tracker entry along with an associated tag value generated when the resolved behaviour was allocated into that cache entry. For a given entry the associated tag value may be generated in dependence on an address indication of the control flow instruction whose resolved behaviour is being stored in that entry and the current active pointer associated with that control flow instruction. Prediction circuitry is responsive to a prediction trigger associated with a replay of a given instance of a given control flow instruction identified by a tracker entry, to cause a lookup operation to be performed by the cache circuitry using a comparison tag value generated in dependence on the address indication of the given control flow instruction and the current active pointer. In the event of a hit being detected in a given cache entry, the resolved behaviour stored in the given cache entry is used as the predicted behaviour of the given instance of the given control flow instruction, provided a prediction confidence metric is met.

公开(公告)号：US20240232228A1

公开(公告)日：2024-07-11

申请号：US18152946

申请日：2023-01-11

Applicant: Arm Limited

Inventor： Thibaut Elie LANOIS ,  Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES

IPC: G06F16/28 ,  G06F16/22 ,  G06F16/2457

CPC classification number: G06F16/285 ,  G06F16/2228 ,  G06F16/24578

Abstract: An apparatus has a data storage structure to store data items tagged by respective tag values and stores, in association with each data item, a respective tag group identifier to identify other data items having a same tag value within a collection of data items. The apparatus also has tag match circuitry to identify one or more hitting data items. Prioritisation circuitry is provided to select candidate data items which, relative to any other data items in the particular collection of data items having the same tag group identifier as the selected candidate data item is favoured according to an ordering of the data items. The prioritisation circuitry selects the one or more candidate data items before the identification of the hitting data items is available from the tag match circuitry. Data item selection circuitry selects a candidate data item for which the tag match circuitry detected a match.

公开(公告)号：US20230214222A1

公开(公告)日：2023-07-06

申请号：US17566157

申请日：2021-12-30

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Thibaut Elie LANOIS ,  Guillaume BOLBENES ,  Jonatan Christoffer LÖVGREN

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3867

Abstract: Aspects of the present disclosure relate to an apparatus. Instruction information generation circuitry generates instruction information. Instruction information storage circuitry comprises a plurality of elements having physical sub-elements configured to temporarily store units of instruction information, Allocation circuitry is configured to receive, from the instruction information generation circuitry, given instruction information, It determines a mapping of a plurality of ordered virtual sub-elements, such that each virtual sub-element maps onto a respective one of said physical sub-elements. The given instruction information is stored into the virtual sub-elements of a given element, according to the mapping, such that at least one virtual sub-element lower in said order has a higher priority than at least one virtual sub-element higher in said order. Sub-element deactivation circuitry is configured to track usage of said virtual sub-elements across the plurality of elements and adaptively deactivate virtual sub-elements.