公开(公告)号：US10133341B2

公开(公告)日：2018-11-20

申请号：US15173939

申请日：2016-06-06

Applicant: ARM Limited

Inventor： Dominic William Brown ,  Ashley John Crawford ,  Christopher Vincent Severino ,  Tessil Thomas

IPC: G06F1/32 ,  G06F13/24

Abstract: An apparatus and a corresponding method of operating the apparatus are disclosed. A component of the apparatus is capable of operating in one of at least two power modes and component power control circuitry which is communicatively coupled to the component causes the component to operate in a selected power mode of those power modes. A system power controller controls operation of the component power control circuitry by setting a power mode lock condition therein. When the power mode lock condition is met the component power control circuitry cannot change the selected power mode of the component. Power control over the component is thus partially delegated from the system power controller to the component power control circuitry.

公开(公告)号：US20230305985A1

公开(公告)日：2023-09-28

申请号：US17702651

申请日：2022-03-23

Applicant: Arm Limited

Inventor： Arthur Brian Laughton ,  Tessil Thomas ,  Jacob Joseph

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4221 ,  G06F13/4063 ,  G06F13/4059 ,  G06F13/1668

Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.

公开(公告)号：US20220206709A1

公开(公告)日：2022-06-30

申请号：US17136510

申请日：2020-12-29

Applicant: Arm Limited

Inventor： Tessil Thomas

IPC: G06F3/06 ,  G06F12/0804

Abstract: Circuitry comprises packet reception circuitry to receive a data communication packet with a storage classification from sending circuitry, the data communication packet including at least payload data and a target address for storage of the payload data; and storage control circuitry to control writing of the payload data of a given data communication packet by one or more storage devices selected from a set of two or more candidate storage devices each addressable by the target address, the storage control circuitry being responsive to the storage classification received with the given data communication packet and to respective persistence properties associated with the set of two or more candidate storage devices.