公开(公告)号：US20230305985A1

公开(公告)日：2023-09-28

申请号：US17702651

申请日：2022-03-23

Applicant: Arm Limited

Inventor： Arthur Brian Laughton ,  Tessil Thomas ,  Jacob Joseph

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4221 ,  G06F13/4063 ,  G06F13/4059 ,  G06F13/1668

Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.

公开(公告)号：US12242399B2

公开(公告)日：2025-03-04

申请号：US17678174

申请日：2022-02-23

Applicant: Arm Limited

Inventor： Jacob Joseph ,  Tessil Thomas ,  Arthur Brian Laughton ,  Anitha Kona ,  Jamshed Jalal

IPC: G06F13/00 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/1045 ,  G06F13/16

Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.

公开(公告)号：US11860811B2

公开(公告)日：2024-01-02

申请号：US17702651

申请日：2022-03-23

Applicant: Arm Limited

Inventor： Arthur Brian Laughton ,  Tessil Thomas ,  Jacob Joseph

IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/1668 ,  G06F13/4059 ,  G06F13/4063

Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.

公开(公告)号：US11803506B2

公开(公告)日：2023-10-31

申请号：US17512758

申请日：2021-10-28

Applicant: Arm Limited

Inventor： Tessil Thomas ,  Anitha Kona ,  Jacob Joseph ,  Arthur Brian Laughton ,  Nandakishore Sastry

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.