公开(公告)号：US10566357B2

公开(公告)日：2020-02-18

申请号：US15837996

申请日：2017-12-11

Applicant: AU OPTRONICS CORPORATION

Inventor： Jia-Hong Ye ,  Ching-Liang Huang

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/04 ,  H01L21/02 ,  H01L29/66

Abstract: The present invention provides a method for crystallizing a metal oxide semiconductor layer, a semiconductor structure, a method for manufacturing a semiconductor structure, an active array substrate, and an indium gallium zinc oxide crystal. The crystallization method includes the following steps: forming an amorphous metal oxide semiconductor layer on a substrate; forming an oxide layer on the amorphous metal oxide semiconductor layer; forming an amorphous silicon layer on the oxide layer; and irradiating the amorphous silicon layer by using a laser, so as to heat the amorphous silicon layer, where the heated amorphous silicon layer heats the amorphous metal oxide semiconductor layer, so that the amorphous metal oxide semiconductor layer is converted into a crystallized metal oxide semiconductor layer.

公开(公告)号：US20190081124A1

公开(公告)日：2019-03-14

申请号：US15839870

申请日：2017-12-13

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye ,  Pin-Fan Wang

IPC: H01L27/32 ,  H01L23/00

Abstract: An array substrate includes a device array, a bonding pad, and at least one support structure. The bonding pad is located in a bonding area and is electrically connected to the device array. A horizontal distance between the at least one support structure and the bonding pad is between 5 μm and 1000 μm.

公开(公告)号：US11362216B2

公开(公告)日：2022-06-14

申请号：US17037698

申请日：2020-09-30

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: An active device substrate includes a substrate, a first active device, and a second active device. The first active device includes a first gate, a crystallized metal oxide layer, a first insulation layer, a first source, and a first drain. The crystallized metal oxide layer is located on the first gate. The first insulation layer is sandwiched between the crystallized metal oxide layer and the first gate. An area from the top surface of the crystallized metal oxide layer to the bottom surface of the crystallized metal oxide layer is observed via a selected area diffraction mode of a transmission electron microscope, and a diffraction pattern of a crystallized phase can be observed. The second active device includes a second gate, a silicon semiconductor layer, a second source, and a second drain. A manufacturing method of an active device substrate is further provided.

公开(公告)号：US11094540B2

公开(公告)日：2021-08-17

申请号：US16368891

申请日：2019-03-29

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye ,  Ching-Liang Huang

IPC: H01L21/02 ,  C23C28/04 ,  H01L27/12 ,  C23C16/24 ,  C23C16/40 ,  C23C16/56 ,  H01L29/786

Abstract: A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided.

公开(公告)号：US10714631B2

公开(公告)日：2020-07-14

申请号：US16575576

申请日：2019-09-19

Applicant: AU OPTRONICS CORPORATION

Inventor： Jia-Hong Ye

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L27/12

Abstract: The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.

公开(公告)号：US20190326440A1

公开(公告)日：2019-10-24

申请号：US16388887

申请日：2019-04-19

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12

Abstract: An active device substrate includes a substrate, a first active device, and a second active device. The first active device includes a first gate, a crystallized metal oxide layer, a first insulation layer, a first source, and a first drain. The crystallized metal oxide layer is located on the first gate. The first insulation layer is sandwiched between the crystallized metal oxide layer and the first gate. An area from the top surface of the crystallized metal oxide layer to the bottom surface of the crystallized metal oxide layer is observed via a selected area diffraction mode of a transmission electron microscope, and a diffraction pattern of a crystallized phase can be observed. The second active device includes a second gate, a silicon semiconductor layer, a second source, and a second drain. A manufacturing method of an active device substrate is further provided.

公开(公告)号：US20190304779A1

公开(公告)日：2019-10-03

申请号：US16368891

申请日：2019-03-29

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye ,  Ching-Liang Huang

IPC: H01L21/02 ,  H01L27/12 ,  C23C28/04

Abstract: A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided.

公开(公告)号：US10312206B2

公开(公告)日：2019-06-04

申请号：US15839870

申请日：2017-12-13

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye ,  Pin-Fan Wang

IPC: H01L23/00 ,  H01L27/32 ,  H01L27/12

Abstract: An array substrate includes a device array, a bonding pad, and at least one support structure. The bonding pad is located in a bonding area and is electrically connected to the device array. A horizontal distance between the at least one support structure and the bonding pad is between 5 μm and 1000 μm.

公开(公告)号：US10007168B2

公开(公告)日：2018-06-26

申请号：US15431911

申请日：2017-02-14

Applicant: AU Optronics Corporation

Inventor： Jia-Hong Ye ,  Hsueh-Fang Yeh

IPC: G02F1/29 ,  G03B13/32

CPC classification number: G02F1/29 ,  G02F1/134309 ,  G02F2001/294 ,  G02F2201/122 ,  G02F2202/10 ,  G03B3/10 ,  G03B13/32 ,  G03B13/34 ,  G03B29/00

Abstract: A liquid crystal lens including a first substrate, a first electrode disposed on the first substrate, a second electrode disposed on the first substrate, a first conductive pattern disposed on the first substrate, a second conductive pattern disposed on the first substrate, a second substrate disposed opposite to the first substrate, a common electrode disposed on the second substrate, and a liquid crystal layer located between the first substrate and the second substrate is provided. The first conductive pattern and the second conductive pattern are electrically connected between the first electrode and the second electrode. A resistivity of the first conductive pattern and a resistivity of the second conductive pattern are greater than a resistivity of the first electrode and a resistivity of the second electrode. At least a portion of the at least one second conductive pattern is disposed into the at least one first conductive pattern.