公开(公告)号：US20210343526A1

公开(公告)日：2021-11-04

申请号：US17375012

申请日：2021-07-14

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye ,  Ching-Liang Huang

IPC: H01L21/02 ,  C23C28/04 ,  H01L27/12

Abstract: A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided.

公开(公告)号：US20170025541A1

公开(公告)日：2017-01-26

申请号：US14938818

申请日：2015-11-11

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye

IPC: H01L29/786 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L21/02422 ,  H01L21/02565 ,  H01L21/02675 ,  H01L21/02686 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78675 ,  H01L29/78678

Abstract: A method of fabricating a thin film transistor including following steps is provided. Sequentially form a semiconductor layer, a metal layer and an auxiliary layer on a substrate. Perform a crystallization process to transform the semiconductor layer into an active layer after the metal layer and the auxiliary layer are disposed on the semiconductor layer. After the active layer is formed, pattern the metal layer to form a source and a drain. Form a gate insulator and a gate. The gate insulator is disposed between the gate and the source and drain.

Abstract translation: 提供一种制造包括以下步骤的薄膜晶体管的方法。 在衬底上依次形成半导体层，金属层和辅助层。 在将金属层和辅助层设置在半导体层上之后，进行结晶处理以将半导体层变换为有源层。 在形成有源层之后，将金属层图案化以形成源极和漏极。 形成栅极绝缘体和栅极。 栅极绝缘体设置在栅极与源极和漏极之间。

公开(公告)号：US20210013344A1

公开(公告)日：2021-01-14

申请号：US17037698

申请日：2020-09-30

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: An active device substrate includes a substrate, a first active device, and a second active device. The first active device includes a first gate, a crystallized metal oxide layer, a first insulation layer, a first source, and a first drain. The crystallized metal oxide layer is located on the first gate. The first insulation layer is sandwiched between the crystallized metal oxide layer and the first gate. An area from the top surface of the crystallized metal oxide layer to the bottom surface of the crystallized metal oxide layer is observed via a selected area diffraction mode of a transmission electron microscope, and a diffraction pattern of a crystallized phase can be observed. The second active device includes a second gate, a silicon semiconductor layer, a second source, and a second drain. A manufacturing method of an active device substrate is further provided.

公开(公告)号：US20200013895A1

公开(公告)日：2020-01-09

申请号：US16575576

申请日：2019-09-19

Applicant: AU OPTRONICS CORPORATION

Inventor： Jia-Hong Ye

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

Abstract: The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.

公开(公告)号：US09577111B2

公开(公告)日：2017-02-21

申请号：US14938818

申请日：2015-11-11

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye

IPC: H01L29/786 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L21/02422 ,  H01L21/02565 ,  H01L21/02675 ,  H01L21/02686 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78675 ,  H01L29/78678

Abstract: A method of fabricating a thin film transistor including following steps is provided. Sequentially form a semiconductor layer, a metal layer and an auxiliary layer on a substrate. Perform a crystallization process to transform the semiconductor layer into an active layer after the metal layer and the auxiliary layer are disposed on the semiconductor layer. After the active layer is formed, pattern the metal layer to form a source and a drain. Form a gate insulator and a gate. The gate insulator is disposed between the gate and the source and drain.

Abstract translation: 提供一种制造包括以下步骤的薄膜晶体管的方法。 在衬底上依次形成半导体层，金属层和辅助层。 在将金属层和辅助层设置在半导体层上之后，进行结晶处理以将半导体层变换为有源层。 在形成有源层之后，将金属层图案化以形成源极和漏极。 形成栅极绝缘体和栅极。 栅极绝缘体设置在栅极与源极和漏极之间。

公开(公告)号：US10969618B1

公开(公告)日：2021-04-06

申请号：US16856050

申请日：2020-04-23

Applicant: Au Optronics Corporation

Inventor： Ssu-Hui Lu ,  Jia-Hong Ye ,  Kuo-Yu Huang

IPC: G02F1/1333 ,  G02F1/1335 ,  G02F1/1362 ,  G06F3/041

Abstract: An opposite substrate including a substrate, first light-shielding patterns, second light-shielding patterns, a planarization layer and support members is provided. The support members are located in primary support regions and secondary support regions of the opposite substrate. The first light-shielding patterns respectively extend along a first direction, and a material of the first light-shielding patterns includes an organic material. The second light-shielding patterns respectively extend along a second direction, and a material of the second light-shielding patterns includes metal. The first light-shielding patterns and the second light-shielding patterns are respectively located at opposite sides of the planarization layer. Alternatively, the first light-shielding patterns and the second light-shielding patterns are located at the same side of the planarization layer, and the planarization layer has openings respectively overlapped with the support members located in the secondary support regions.

公开(公告)号：US10446691B2

公开(公告)日：2019-10-15

申请号：US15635989

申请日：2017-06-28

Applicant: AU OPTRONICS CORPORATION

Inventor： Jia-Hong Ye

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12

Abstract: The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.

公开(公告)号：US09252167B2

公开(公告)日：2016-02-02

申请号：US14486069

申请日：2014-09-15

Applicant: AU Optronics Corporation

Inventor： Jia-Hong Ye ,  Ssu-Hui Lu ,  Wu-Hsiung Lin ,  Chao-Chien Chiu ,  Ming-Hsien Lee ,  Chia-Tien Peng ,  Wei-Ming Huang

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1255 ,  H01L27/1218 ,  H01L27/1248 ,  H01L29/78603

Abstract: An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has a transistor region and a transparent region adjacent to each other. The gate electrode is disposed on the transistor region. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region has a second thickness less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are electrically connected to the channel layer. The pixel electrode is disposed on the dielectric layer which is disposed on the transparent region. The pixel electrode is electrically connected to the drain electrode.

Abstract translation: 有源器件阵列衬底包括柔性衬底，栅电极，电介质层，沟道层，源电极，漏电极和像素电极。 柔性基板具有彼此相邻的晶体管区域和透明区域。 栅电极设置在晶体管区域上。 电介质层覆盖柔性基板和栅电极。 布置在栅电极上的介电层的一部分具有第一厚度。 布置在透明区域上的介电层的另一部分具有小于第一厚度的第二厚度。 沟道层设置在栅电极的上方。 源电极和漏极电连接到沟道层。 像素电极设置在布置在透明区域上的电介质层上。 像素电极电连接到漏电极。

公开(公告)号：US11467458B1

公开(公告)日：2022-10-11

申请号：US17506652

申请日：2021-10-20

Applicant: Au Optronics Corporation

Inventor： Jia-Hong Ye ,  Kuo-Yu Huang

IPC: G02F1/1362 ,  G02F1/1343

Abstract: A circuit substrate includes a substrate, an active device, a first signal line, a second signal line, a shielding electrode, a data line, a pixel electrode, and a common electrode. The first signal line is electrically connected to the active device, and includes a main portion and a connection portion connected to the main portion. The main portion extends along a first direction. The second signal line extends along a second direction. The second signal line is electrically connected to the connection portion. The shielding electrode overlaps the connection portion in a normal direction of the substrate. The shielding electrode and the second signal line belong to a same conductive layer. The data line is electrically connected to the active device. The common electrode is electrically connected to the shielding electrode.

公开(公告)号：US11134346B2

公开(公告)日：2021-09-28

申请号：US16991074

申请日：2020-08-12

Applicant: AU OPTRONICS CORPORATION

Inventor： Jia-Hong Ye ,  Cheng-Syun Sie

IPC: H04R1/02 ,  H04R17/00 ,  F21V8/00 ,  H04R7/04

Abstract: A backlight module and display device using the same are provided. The backlight module has a light guide plate. A piezoelectric module is arranged at the outer side of the backside surface of the light guide plate and configured to produce a vibration. The vibration is directly or indirectly transmitted to a resonator, for example, a light guide plate or a bezel, to produce resonance, and a space to which the backside surface is oriented is used as a resonance cavity. By means of the arrangement, the screen-to-body ratio of electronic products and the sound quality can be improved while taking into account the thickness and volume of the electronic products.