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公开(公告)号：US20190066622A1
公开(公告)日：2019-02-28
申请号：US16111531
申请日：2018-08-24
Applicant: AU Optronics Corporation
Inventor： Yi-Cheng LIN , Ming-Hsien Lee , Kai-Wei Hong , Chun-Da Tu , Chuang-Cheng Yang , Chun-Feng Lin
IPC: G09G3/36
Abstract: A multiplexer applied to a display device includes: a plurality of switching units, electrically coupled to a data driver and a plurality of pixel units, where the switching units are adapted to receive a plurality of input display data signals output by the data driver, and the switching units output a plurality of output display data signals to the electrically coupled pixel units, where each of the switching units includes a plurality of switch units, configuration locations of the switch units in each of the switching units are the same as, and some of the switch units configured at a same configuration location in the different switching units are electrically coupled to different control signal lines and have different wiring lengths, where the wiring lengths are distances between the switch units and the control signal lines.
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公开(公告)号：US10152913B1
公开(公告)日：2018-12-11
申请号：US15830386
申请日：2017-12-04
Applicant: AU Optronics Corporation
Inventor： Yi-Cheng Lin , Ming-Hsien Lee , Kai-Wei Hong , Chun-Da Tu , Chuang-Cheng Yang , Chun-Feng Lin
IPC: G09G3/20
Abstract: An anti-interference display panel includes a source driving chip, a switching signal line, a multiplexer, and an anti-interference signal line. The source driving chip is configured to generate a data signal. The switching signal line is configured to transmit a switching signal. The multiplexer is configured to receive the data signal and the switching signal, and is configured to output the data signal according to the switching signal. The anti-interference signal line is configured to transmit an anti-interference signal. An equivalent resistor and an equivalent capacitor are formed on the anti-interference signal line, and resistance of the equivalent resistor is approximate to resistance of a load resistor coupled to the switching signal line, and capacitance of the equivalent capacitor is approximate to capacitance of a load capacitor coupled to the switching signal line. A voltage of the anti-interference signal falls when a voltage of the switching signal rises, and rises when the voltage of the switching signal falls.
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公开(公告)号：US10930239B2
公开(公告)日：2021-02-23
申请号：US16690606
申请日：2019-11-21
Applicant: AU Optronics Corporation
Inventor： Kai-Wei Hong , Chun-Da Tu , Ming-Hsien Lee , Chuang-Cheng Yang , Yi-Cheng Lin , Chun-Feng Lin
Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.
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公开(公告)号：US10522105B2
公开(公告)日：2019-12-31
申请号：US15953720
申请日：2018-04-16
Applicant: AU Optronics Corporation
Inventor： Kai-Wei Hong , Chun-Da Tu , Ming-Hsien Lee , Chuang-Cheng Yang , Yi-Cheng Lin , Chun-Feng Lin
Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.
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Patent Agency Ranking
公开(公告)号：US20190355754A1
公开(公告)日：2019-11-21
申请号：US16527002
申请日：2019-07-30
Applicant: Au Optronics Corporation
Inventor： Cheng-Kuang Wang , Chun-Da Tu
Abstract: A display panel including a display region and a non-display region, a plurality of gate lines, a plurality of data lines, a pixel array and a gate on array circuit. The non-display region is located at one side of the display region. The plurality of gate lines and the plurality of data lines are disposed in the display region. The pixel array is located in the display region, wherein the pixel array is composed of a plurality of pixel units that are repeatedly arranged. The pixel units consist of three gate lines, two data lines and six sub-pixels, and each sub-pixel is electrically connected to one of the gate lines and one of the data lines located in the pixel array respectively. The gate on array circuit is disposed in the pixel array.
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公开(公告)号：US20190064978A1
公开(公告)日：2019-02-28
申请号：US16008039
申请日：2018-06-14
Applicant: Au Optronics Corporation
Inventor： Chun-Da Tu , Ming-Hsien Lee , Kai-Wei Hong , Chuang-Cheng Yang , Yi-Cheng Lin , Chun-Feng Lin
Abstract: A shift register and a touch display apparatus thereof are provided. The shift register includes a voltage setting unit, a driving unit, a control unit, a discharge unit, a first compensation transistor, and a second compensation transistor. The voltage setting unit sets a terminal voltage of an internal terminal. The driving unit is coupled to the internal terminal to provide a gate signal and a driving signal. The control unit receives the terminal voltage to provide a control signal. The discharge unit discharges the terminal voltage and the gate signal according to the control signal. The first compensation transistor and the second compensation transistor are coupled in series between a touch enable signal and the internal terminal, and control terminals of the first compensation transistor and the second compensation transistor receive the terminal voltage and the touch enable signal, respectively.
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公开(公告)号：US10019956B2
公开(公告)日：2018-07-10
申请号：US15139827
申请日：2016-04-27
Applicant: AU OPTRONICS CORPORATION
Inventor： Chun-Da Tu , Yung-Chih Chen , Cheng-Han Huang , Kai-Wei Hong , Hsiang-Sheng Chang , Chuang-Cheng Yang
CPC classification number: G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2320/0214 , G11C19/28
Abstract: A shift register including a voltage set unit, a driver unit, a control unit, a first transistor, a second transistor, a third transistor and a fourth transistor is provided. The voltage set unit provides a terminal voltage. The driver unit provides a main gate signal according to the terminal voltage and a clock signal. The control unit provides a control signal. The first transistor receives the terminal voltage, a level reference voltage and the control signal. The second transistor is coupled to the first transistor and receives a low voltage and the control signal. The third transistor receives the terminal voltage, a level reference voltage and a gate reference signal. The fourth transistor is coupled to the third transistor and receives the low voltage and the gate reference signal.
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公开(公告)号：US20170124971A1
公开(公告)日：2017-05-04
申请号：US15139827
申请日：2016-04-27
Applicant: AU OPTRONICS CORPORATION
Inventor： Chun-Da Tu , Yung-Chih Chen , Cheng-Han Huang , Kai-Wei Hong , Hsiang-Sheng Chang , Chuang-Cheng Yang
CPC classification number: G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2320/0214 , G11C19/28
Abstract: A shift register including a voltage set unit, a driver unit, a control unit, a first transistor, a second transistor, a third transistor and a fourth transistor is provided. The voltage set unit provides a terminal voltage. The driver unit provides a main gate signal according to the terminal voltage and a clock signal. The control unit provides a control signal. The first transistor receives the terminal voltage, a level reference voltage and the control signal. The second transistor is coupled to the first transistor and receives a low voltage and the control signal. The third transistor receives the terminal voltage, a level reference voltage and a gate reference signal. The fourth transistor is coupled to the third transistor and receives the low voltage and the gate reference signal.
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公开(公告)号：US09454942B2
公开(公告)日：2016-09-27
申请号：US14644692
申请日：2015-03-11
Applicant: AU Optronics Corporation
Inventor： Chih-Lung Lin , Yuan-Wei Du , Fu-Hsing Chen , Chun-Da Tu
IPC: G09G3/36 , H03K19/0185
CPC classification number: G09G3/3677 , G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2310/0289 , H03K19/018507
Abstract: A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N−1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit.
Abstract translation: 显示面板包括栅极线和栅极驱动器。 栅极驱动器包括串联耦合驱动级，其中串联耦合驱动级的第N驱动级包括驱动单元和输入控制单元。 驱动单元根据控制节点的控制电压电平发送第一时钟信号，以输出栅极驱动信号。 输入控制单元将从第（N-1）驱动级输出的栅极驱动信号发送到控制节点，以将控制电压电平调整为第一电压电平和第二电压电平之一。 在第一时钟信号的上升沿和第二时钟信号的下降沿之间存在预定的时间间隔。 在预定时间间隔期间，通过输入控制单元将控制电压电平拉至第一电压电平。
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