公开(公告)号：US20180026917A1

公开(公告)日：2018-01-25

申请号：US15218681

申请日：2016-07-25

Applicant: Adee O. Ran ,  David L. Chalupsky ,  Kevan A. Lillie ,  Richard I. Mellitz ,  Kent C. Lusted

Inventor： Adee O. Ran ,  David L. Chalupsky ,  Kevan A. Lillie ,  Richard I. Mellitz ,  Kent C. Lusted

IPC: H04L12/935

CPC classification number: H04L49/3054

Abstract: Methods and apparatus for Ethernet auto-negotiation (AN) with parallel detect for 10G DAC or other non-auto-negotiated modes. AN base pages are transmitted from an Ethernet apparatus to advertise the ability to support at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting AN. A receiver and associated processing circuitry is configured to perform two detection modes in parallel, including a first detection mode that looks for a valid signal transmitted from an Ethernet link peer that does not support AN and a second detection mode looking for AN pages from an IEEE 802.3 Ethernet link peer that supports AN. If the link peer does not support AN, an Ethernet link is set up to use signaling in accordance with the Ethernet specification that does not support AN. If the link peer supports AN, an Ethernet link is set up using a corresponding IEEE 802.3 Ethernet link supporting AN. Supported non-AN Ethernet links include 10G DAC links.

公开(公告)号：US20160099795A1

公开(公告)日：2016-04-07

申请号：US14580731

申请日：2014-12-23

Applicant: Kent C. Lusted ,  Adee O. Ran ,  Richard I. Mellitz

Inventor： Kent C. Lusted ,  Adee O. Ran ,  Richard I. Mellitz

IPC: H04L1/00 ,  G06F11/10

CPC classification number: H04L1/0041 ,  G06F11/10 ,  H04L1/0009 ,  H04L1/0023

Abstract: Technologies for capabilities exchange include a network port logic having a communication link coupled to a remote link partner. The port logic transmits local host loss information to the link partner and receives remote host loss information from the link partner. The port logic may communicate the host loss information via an autonegotiation base page, an autonegotiation next page, or a PMD control frame. The port logic determines total channel loss based on the local host loss, the remote host loss, and cable loss. The port logic may bring the communication link up without forward error correction (FEC) if the total channel loss is less than a FEC limit, may bring the link up with FEC if the total loss is less than a specification limit, or may not bring the link up if the total channel loss is above the specification limit. Other embodiments are described and claimed.

Abstract translation: 用于能力交换的技术包括具有耦合到远程链路伙伴的通信链路的网络端口逻辑。 端口逻辑将本地主机丢失信息传输到链路伙伴，并从链路伙伴接收远程主机丢失信息。 端口逻辑可以经由自动协商基页，自动协商下一页或PMD控制帧来传送主机丢失信息。 端口逻辑基于本地主机丢失，远程主机丢失和电缆丢失来确定总信道丢失。 如果总信道损失小于FEC限制，则端口逻辑可以使通信链路上升而不进行前向纠错（FEC），如果总损耗小于规范限制，则可以使链路成为FEC，否则可能不带 如果总频道损失高于规格限制，则链接。 描述和要求保护其他实施例。

公开(公告)号：US20160087753A1

公开(公告)日：2016-03-24

申请号：US14580737

申请日：2014-12-23

Applicant: Adee O. Ran ,  Kent C. Lusted

Inventor： Adee O. Ran ,  Kent C. Lusted

IPC: H04L1/00 ,  H04L12/28 ,  G06F11/10 ,  H04L12/825

CPC classification number: H04L45/66 ,  H03M13/25 ,  H03M13/251 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0083

Abstract: Technologies for high-speed data transmission include a network port logic having one or more communication lanes coupled to a forward error correction (FEC) sublayer and a physical coding sublayer (PCS). To transmit data, the PCS encodes the data to be transmitted into encoded data blocks using a 66b/64b line code and inserts alignment marker blocks after every 16,383 encoded data blocks. The FEC encodes the encoded data blocks into 80-block FEC codewords starting at a predefined offset from an alignment marker. Thus, each alignment marker is at one of five predefined offsets from the beginning of an FEC codeword. Each alignment marker may include a unique block type field usable with FEC encoding. The PCS may include one or more logical lanes, each operating at 25 Gb/s. Embodiments of the network port logic may include a single PCS lane or sixteen PCS lanes. Other embodiments are described and claimed.

Abstract translation: 用于高速数据传输的技术包括具有耦合到前向纠错（FEC）子层和物理编码子层（PCS））的一个或多个通信通道的网络端口逻辑。 为了发送数据，PCS使用66b / 64b行代码将要发送的数据编码为编码数据块，并在每16383个编码数据块之后插入对准标记块。 FEC将经编码的数据块编码为从对准标记的预定偏移开始的80块FEC码字。 因此，每个对准标记是从FEC码字开头的五个预定偏移量之一。 每个对准标记可以包括可用于FEC编码的唯一块类型字段。 PCS可以包括一个或多个逻辑通道，每个逻辑通道以25Gb / s工作。 网络端口逻辑的实施例可以包括单个PCS通道或十六个PCS车道。 描述和要求保护其他实施例。

公开(公告)号：US20150256366A1

公开(公告)日：2015-09-10

申请号：US14583663

申请日：2014-12-27

Applicant: Adee O. Ran

Inventor： Adee O. Ran

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  B01D3/009 ,  C07C51/265 ,  C07C63/26 ,  C08G63/183

Abstract: Technologies for transmitter equalization in a communication system include reading local transmitter equalization settings from a transmitter equalization register of a first communication device and writing the local transmitter equalization settings to a transmitter equalization register of a second communication device communicatively coupled with the first communication device via a chip-to-chip communication link. Additionally, requested transmitter equalization settings may be read from the transmitter equalization register of the second communication device and written to the transmitter equalization register of the first communication device. The reading and writing process may be repeated for the opposite communication direction and for other communication lane interfaces of the first and second communication devices.

Abstract translation: 在通信系统中用于发射机均衡的技术包括从第一通信设备的发射机均衡寄存器读取本地发射机均衡设置，并将本地发射机均衡设置写入到与第一通信设备通信耦合的第二通信设备的发射机均衡寄存器 芯片到芯片的通信链路。 此外，可以从第二通信设备的发射机均衡寄存器读取所请求的发射机均衡设置，并将其写入第一通信设备的发射机均衡寄存器。 可以针对相对的通信方向和第一和第二通信设备的其他通信通道接口重复读取和写入过程。

公开(公告)号：US08861578B1

公开(公告)日：2014-10-14

申请号：US13926035

申请日：2013-06-25

Applicant: Kent C. Lusted ,  Adee O. Ran

Inventor： Kent C. Lusted ,  Adee O. Ran

IPC: H04B3/46 ,  H04L25/49 ,  H04B17/00

CPC classification number: H04L25/4917 ,  H04B17/0085 ,  H04B17/104

Abstract: Methods, apparatus and systems for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter. During a test procedure, a PAM4 transmitter is configured to repetitively transmitting a four-level test pattern, which is captured and digitized. The digitized data is processed to generate a linear-fitted waveform. A voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level is measured and used to derive 20% and 80% VMA levels in an eye diagram. The rise transition time is then determined by measuring the time interval between when a rising signal crosses the 20% and 80% VMA levels, and the fall transition time is determined by measuring the time interval between when a falling signal crosses the 80% and 20% VMA levels.

Abstract translation: 用于测量四电平脉冲调制幅度（PAM4）发射机的信号转换时间的方法，装置和系统。 在测试过程中，PAM4发射机被配置为重复地发送被采集和数字化的四级测试模式。 处理数字化数据以生成线性拟合波形。 测量-1和+1 PAM4信号电平中的每一个的电压调制幅度（VMA）电平，并用于在眼图中导出20％和80％的VMA电平。 然后通过测量上升信号跨越20％和80％VMA电平之间的时间间隔来确定上升过渡时间，并且通过测量下降信号跨越80％和20之间的时间间隔来确定下降转变时间 ％VMA级别。

公开(公告)号：US20140161141A1

公开(公告)日：2014-06-12

申请号：US13758259

申请日：2013-02-04

Applicant: Kent C. Lusted ,  Adee O. Ran

Inventor： Kent C. Lusted ,  Adee O. Ran

IPC: H04L12/24

CPC classification number: H04L12/12 ,  H04L12/40039 ,  H04L12/40136 ,  Y02D50/10 ,  Y02D50/40 ,  Y02D50/42

Abstract: Methods, apparatus and systems for implementing for implementing Energy-Efficient Ethernet (EEE) refresh and wake signaling for high-speed Ethernet links. During an EEE refresh or wake signaling period, ALERT frames are transmitted between first and second Ethernet interfaces on opposing ends of the link, with a first ALERT frame being sent from a first Ethernet interface and a second ALERT frame being returned from the second Ethernet interface. The ALERT frames have a length that is different that the length of Physical Media Attachment (PMA) frames, and the returned ALERT frames include frame alignment offset data identifying a relative offset between an ALERT frame and a predetermined location in a PMA frame, and countdown data. The frame alignment offset data and countdown data are employed to facilitate a rapid transition from the link training mode to the data mode.

Abstract translation: 用于实现高速以太网链路的高效以太网（EEE）刷新和唤醒信号的实现方法，装置和系统。 在EEE刷新或唤醒信令期间，ALERT帧在链路的相对端的第一和第二以太网接口之间传输，第一ALERT帧从第一以太网接口发送，第二ALERT帧从第二以太网接口返回 。 ALERT帧的长度与物理媒体附件（PMA）帧的长度不同，并且返回的ALERT帧包括标识ALERT帧和PMA帧中的预定位置之间的相对偏移的帧对准偏移数据，以及倒计时 数据。 采用帧对准偏移数据和倒计数数据来促进从链接训练模式到数据模式的快速转变。

公开(公告)号：US20160182175A1

公开(公告)日：2016-06-23

申请号：US14574482

申请日：2014-12-18

Applicant: Yoni Landau ,  Assaf Benhamou ,  Adee O. Ran

Inventor： Yoni Landau ,  Assaf Benhamou ,  Adee O. Ran

IPC: H04J3/06 ,  H04L7/04

CPC classification number: H04J3/0658 ,  H04L7/041 ,  H04L12/12 ,  H04L2007/045 ,  Y02D50/40 ,  Y02D50/42

Abstract: Technologies for robust data transmission include a network port logic having a physical coding sublayer (PCS). The PCS may transmit a series of rapid alignment markers (RAMs) to a link partner, with each RAM indicative of a counter value. The PCS transitions to a sleep state if the counter value equals two and a low power idle (LPI) command is set by an upper-layer client. The PCS transitions to an active state if the counter value equals one and the LPI command is not set. The PCS may receive a low power idle symbol (LI) from the link partner and start a guard timer in response to receipt of the LI symbol. The PCS transitions to a sleep state if the guard timer expires and transitions to the active state if data other than LI is received prior to expiration of the guard timer. Other embodiments are described and claimed.

Abstract translation: 用于鲁棒数据传输的技术包括具有物理编码子层（PCS）的网络端口逻辑。 PCS可以将一系列快速对准标记（RAM）发送到链路伙伴，每个RAM指示计数器值。 如果计数器值等于2，并且上层客户端设置了低功耗空闲（LPI）命令，则PCS转换到睡眠状态。 如果计数器值等于1并且未设置LPI命令，则PCS将转换到活动状态。 PCS可以从链路伙伴接收低功率空闲符号（LI），并且响应于LI符号的接收而启动保护定时器。 如果保护定时器到期，则PCS转换到睡眠状态，并且如果在保护定时器到期之前接收到除L1之外的数据，则转换到活动状态。 描述和要求保护其他实施例。

公开(公告)号：US20160124034A1

公开(公告)日：2016-05-05

申请号：US14527560

申请日：2014-10-29

Applicant: Ehud Udi Shoor ,  Dror Lazar ,  Adee O. Ran

Inventor： Ehud Udi Shoor ,  Dror Lazar ,  Adee O. Ran

IPC: G01R31/02 ,  G01M11/00

CPC classification number: G01R31/021 ,  G01M11/33 ,  H04B3/36 ,  H04B3/46

Abstract: Embodiments of the present disclosure provide configurations for testing arrangements for testing multi-lane active cables. In one embodiment, a testing arrangement may comprise a testing module comprising a pattern generator to be coupled with an active cable having a plurality of lanes to generate a test pattern to be transmitted over the active cable, wherein the test pattern is to be transmitted at least over two or more lanes of the active cable that are concatenated, and a processing unit to be coupled with the active cable to process a result of the transmission of the test pattern over the active cable. The arrangement may further include a plurality of testing cables to concatenate two or more of the lanes of the active cable, to enable the transmission of the test pattern over the concatenated lanes of the active cable. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了用于测试多通道有源电缆的测试布置的配置。 在一个实施例中，测试装置可以包括测试模块，该测试模块包括与具有多个通道的有源电缆耦合的模式发生器，以产生将通过有源电缆传输的测试模式，其中测试模式将以 串联的有源电缆的至少两个或更多个通道，以及与有源电缆耦合以处理测试图案在有源电缆上传输的结果的处理单元。 该布置还可以包括多个测试电缆，以连接有源电缆的两条或更多条通道，以使测试图案能够在有源电缆的级联通道上传输。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09264267B2

公开(公告)日：2016-02-16

申请号：US14583663

申请日：2014-12-27

Applicant: Adee O. Ran

Inventor： Adee O. Ran

IPC: H04L25/03 ,  B01D3/00 ,  C07C51/265 ,  C07C63/26 ,  C08G63/183

CPC classification number: H04L25/03885 ,  B01D3/009 ,  C07C51/265 ,  C07C63/26 ,  C08G63/183

Abstract: Technologies for transmitter equalization in a communication system include reading local transmitter equalization settings from a transmitter equalization register of a first communication device and writing the local transmitter equalization settings to a transmitter equalization register of a second communication device communicatively coupled with the first communication device via a chip-to-chip communication link. Additionally, requested transmitter equalization settings may be read from the transmitter equalization register of the second communication device and written to the transmitter equalization register of the first communication device. The reading and writing process may be repeated for the opposite communication direction and for other communication lane interfaces of the first and second communication devices.

Abstract translation: 在通信系统中用于发射机均衡的技术包括从第一通信设备的发射机均衡寄存器读取本地发射机均衡设置，并将本地发射机均衡设置写入到与第一通信设备通信耦合的第二通信设备的发射机均衡寄存器 芯片到芯片的通信链路。 此外，可以从第二通信设备的发射机均衡寄存器读取所请求的发射机均衡设置，并将其写入第一通信设备的发射机均衡寄存器。 可以针对相对的通信方向和第一和第二通信设备的其他通信通道接口重复读取和写入过程。

公开(公告)号：US20140380132A1

公开(公告)日：2014-12-25

申请号：US13926041

申请日：2013-06-25

Applicant: Adee O. Ran

Inventor： Adee O. Ran

IPC: H04L1/00

CPC classification number: H04L1/0045 ,  H04L1/0038 ,  H04L1/0057 ,  H04L1/203 ,  H04L1/245

Abstract: Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. Under one aspect, correctable symbol errors are detected, and determination is made to whether a symbol error rate or ratio (SER) exceeds an SER threshold. In response to detection of such a condition, the link is disconnected or temporarily paused. The value for the SER threshold is determined using a statistical analysis of various link parameters to meet desired performance levels, such as a mean time to false packet acceptance (MTTFPA) of >approximately 15 billion years while providing a mean time to disconnect of >100 years.

Abstract translation: 用于在高速链路中防止虚假包接收的方法，装置和系统。 在一个方面，检测到可校正的符号错误，并且确定符号错误率或比率（SER）是否超过SER阈值。 响应于这种情况的检测，链路断开或暂时暂停。 使用各种链路参数的统计分析来确定SER阈值的值，以满足期望的性能水平，例如>大约150亿年的假包接收的平均时间（MTTFPA），同时提供断开> 100的平均时间 年份。