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    Technique for switching between 1x and 2x oversampling rate in a TD-SCDMA receiver
    11.
    发明授权
    Technique for switching between 1x and 2x oversampling rate in a TD-SCDMA receiver 有权
    在TD-SCDMA接收机中切换1x和2x过采样率的技术

    公开(公告)号：US08548005B2

    公开(公告)日：2013-10-01

    申请号：US13090223

    申请日：2011-04-19

    申请人： Yonggang Hao ,  Aiguo Yan ,  Songsong Sun ,  Marko Kocic

    发明人： Yonggang Hao ,  Aiguo Yan ,  Songsong Sun ,  Marko Kocic

    IPC分类号： H04J13/00

    CPC分类号： H04B1/7105

    摘要： A TD-SCDMA receiver is provided that includes a joint detection (JD) block receiving a first input signal from a channel estimation block for signal detection. A short channel detection (SCD) block receives the first input signal and detecting the presence/absence of an AGWN-like channel based on the first input signal from the channel estimation block. The SCD block switches the JD block between 1× and 2× oversampling rates by sending to the JD block a second input signal.

    摘要翻译： 提供一种TD-SCDMA接收机，其包括从用于信号检测的信道估计块接收第一输入信号的联合检测（JD）块。 短信道检测（SCD）块基于来自信道估计块的第一输入信号接收第一输入信号并检测AGWN样信道的存在/不存在。 SCD块通过向JD块发送第二个输入信号来将JD块切换到1×和2×过采样率之间。

    ADVANCED JOINT DETECTION IN A TD-SCDMA SYSTEM
    12.
    发明申请
    ADVANCED JOINT DETECTION IN A TD-SCDMA SYSTEM 有权
    TD-SCDMA系统中的高级联合检测

    公开(公告)号：US20130070833A1

    公开(公告)日：2013-03-21

    申请号：US13235462

    申请日：2011-09-18

    申请人： Aiguo Yan ,  Yonggang Hao ,  Marko Kocic

    发明人： Aiguo Yan ,  Yonggang Hao ,  Marko Kocic

    IPC分类号： H04L27/06 ,  H03K5/00

    CPC分类号： H04L25/0212 ,  H04L25/03038 ,  H04L25/03834

    摘要： A communication system is provided that includes a composite transfer module that receives an input signal and performs one or more selective operations defined by a first transfer function on the input signal. The composite transfer module outputs a first signal. A joint detection module receives the first signal and performs joint detection on the first signal. The joint detection module utilizes channel estimation information of the first transfer function so as to allow the joint detection module to perform joint detection with an oversampling rate of 2× or higher.

    摘要翻译： 提供了一种通信系统，其包括复合传送模块，其接收输入信号并执行由输入信号上的第一传递函数定义的一个或多个选择性操作。 复合传送模块输出第一信号。 联合检测模块接收第一信号并对第一信号进行联合检测。 联合检测模块利用第一传递函数的信道估计信息，以使联合检测模块以2×以上的过采样率进行联合检测。

    Advanced joint detection in a TD-SCDMA system
    13.
    发明授权
    Advanced joint detection in a TD-SCDMA system 有权
    TD-SCDMA系统高级联合检测

    公开(公告)号：US08711986B2

    公开(公告)日：2014-04-29

    申请号：US13235462

    申请日：2011-09-18

    申请人： Aiguo Yan ,  Yonggang Hao ,  Marko Kocic

    发明人： Aiguo Yan ,  Yonggang Hao ,  Marko Kocic

    IPC分类号： H04L27/06 ,  H04B1/10

    CPC分类号： H04L25/0212 ,  H04L25/03038 ,  H04L25/03834

    摘要： A communication system is provided that includes a composite transfer module that receives an input signal and performs one or more selective operations defined by a first transfer function on the input signal. The composite transfer module outputs a first signal. A joint detection module receives the first signal and performs joint detection on the first signal. The joint detection module utilizes channel estimation information of the first transfer function so as to allow the joint detection module to perform joint detection with an oversampling rate of 2× or higher.

    摘要翻译： 提供了一种通信系统，其包括复合传送模块，其接收输入信号并执行由输入信号上的第一传递函数定义的一个或多个选择性操作。 复合传送模块输出第一信号。 联合检测模块接收第一信号并对第一信号进行联合检测。 联合检测模块利用第一传递函数的信道估计信息，以使联合检测模块以2×以上的过采样率进行联合检测。

    ACTIVE CODE SELECTION FOR JOINT-DETECTION BASED TDSCDMA RECEIVER
    14.
    发明申请
    ACTIVE CODE SELECTION FOR JOINT-DETECTION BASED TDSCDMA RECEIVER 审中-公开
    基于联合检测的TDSCDMA接收机的主动代码选择

    公开(公告)号：US20120257548A1

    公开(公告)日：2012-10-11

    申请号：US13109009

    申请日：2011-05-17

    申请人： Aiguo Yan ,  Hengsheng Tang ,  Yonggang Hao ,  Min Lei ,  Marko Kocic

    发明人： Aiguo Yan ,  Hengsheng Tang ,  Yonggang Hao ,  Min Lei ,  Marko Kocic

    IPC分类号： H04L5/14 ,  H04J13/00

    CPC分类号： H04B1/71052

    摘要： A TD-SCDMA receiver includes a joint detector that receives an input signal from a transceiver. The joint detector analyzes the input signal to using an active code selection (ACS) to determine whether one or more neighboring cells are used in conjunction with a servicing cell. Also, the ACS assigns a first matrix that includes necessary active coded channels including those associated with the one or neighboring cells so as to formulate a channel matrix.

    摘要翻译： TD-SCDMA接收机包括从收发机接收输入信号的联合检测器。 联合检测器分析输入信号以使用活动码选择（ACS）来确定一个或多个相邻小区是否与服务小区一起使用。 此外，ACS分配包括必需的活动编码信道的第一矩阵，包括与一个或相邻小区相关联的那些，以便制定信道矩阵。

    Interface between chip rate processing and bit rate processing in wireless downlink receiver
    15.
    发明申请
    Interface between chip rate processing and bit rate processing in wireless downlink receiver 有权
    无线下行接收机芯片速率处理与比特率处理之间的接口

    公开(公告)号：US20080080443A1

    公开(公告)日：2008-04-03

    申请号：US11529146

    申请日：2006-09-28

    申请人： Lidwine Martinot ,  Deepak Mathew ,  Krishnan Vishwanathan ,  Eric Aardoom ,  Aiguo Yan ,  Timothy Fisher-Jeffes

    发明人： Lidwine Martinot ,  Deepak Mathew ,  Krishnan Vishwanathan ,  Eric Aardoom ,  Aiguo Yan ,  Timothy Fisher-Jeffes

    IPC分类号： H04B7/216

    CPC分类号： H04B1/7105 ,  H04B2201/70707

    摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.

    摘要翻译： 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器， 以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。 后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收 解码的传输信道位。

    Architecture for downlink receiver bit rate processor
    16.
    发明申请
    Architecture for downlink receiver bit rate processor 审中-公开
    下行接收器比特率处理器的架构

    公开(公告)号：US20080080542A1

    公开(公告)日：2008-04-03

    申请号：US11529148

    申请日：2006-09-28

    申请人： Krishnan Vishwanathan ,  Deepak Mathew ,  Eric Aardoom ,  Lidwine Martinot ,  Aiguo Yan ,  Timothy Fisher-Jeffes ,  Paul D. Krivacek

    发明人： Krishnan Vishwanathan ,  Deepak Mathew ,  Eric Aardoom ,  Lidwine Martinot ,  Aiguo Yan ,  Timothy Fisher-Jeffes ,  Paul D. Krivacek

    IPC分类号： H04L12/56

    CPC分类号： H04B1/707 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0054 ,  H04L1/0067

    摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.

    摘要翻译： 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器， 以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。 后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收 解码的传输信道位。

    Interface between chip rate processing and bit rate processing in wireless downlink receiver
    17.
    发明授权
    Interface between chip rate processing and bit rate processing in wireless downlink receiver 有权
    无线下行接收机芯片速率处理与比特率处理之间的接口

    公开(公告)号：US08358988B2

    公开(公告)日：2013-01-22

    申请号：US11529146

    申请日：2006-09-28

    申请人： Lidwine Martinot ,  Deepak Mathew ,  Krishnan Vishwanathan ,  Eric Aardoom ,  Aiguo Yan ,  Timothy Fisher-Jeffes

    发明人： Lidwine Martinot ,  Deepak Mathew ,  Krishnan Vishwanathan ,  Eric Aardoom ,  Aiguo Yan ,  Timothy Fisher-Jeffes

    IPC分类号： H04B1/18

    CPC分类号： H04B1/7105 ,  H04B2201/70707

    摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.

    摘要翻译： 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级 并且提供编码的传输信道数据。 后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。

    Method and system for blind channel impulse response combining for noise mitigation in channel estimation in a TD-SCDMA receiver
    20.
    发明授权
    Method and system for blind channel impulse response combining for noise mitigation in channel estimation in a TD-SCDMA receiver 有权
    TD-SCDMA接收机信道估计中用于噪声抑制的盲信道脉冲响应组合方法和系统

    公开(公告)号：US08929344B2

    公开(公告)日：2015-01-06

    申请号：US13314159

    申请日：2011-12-07

    申请人： Yonggang Hao ,  Jianwei Zhang ,  Aiguo Yan ,  Songsong Sun

    发明人： Yonggang Hao ,  Jianwei Zhang ,  Aiguo Yan ,  Songsong Sun

    IPC分类号： H04B7/216 ,  H04L25/02

    CPC分类号： H04L25/0204 ,  H04L25/0212 ,  H04L25/0216 ,  H04L25/0238

    摘要： Blind channel impulse response combining for noise mitigation in channel estimation in a TD-SCDMA receiver includes applying a correlation function to pairs of channel impulse response windows associated with non-desired user equipments, grouping all those channel impulse response windows having a correlation function above a predetermined threshold as identified with the same user equipment, and combining the channel estimation results from each identified user equipment in the group to mitigate noise.

    摘要翻译： 用于TD-SCDMA接收机的信道估计中用于噪声抑制的盲信道脉冲响应组合包括将相关函数应用于与非期望用户设备相关联的信道脉冲响应窗口对，将具有高于1的相关函数的所有那些信道脉冲响应窗口分组 用相同的用户设备识别的预定阈值，以及组合来自组中每个识别的用户设备的信道估计结果以减轻噪声。