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公开(公告)号：US06848094B2
公开(公告)日：2005-01-25
申请号：US10334731
申请日：2002-12-31
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method of global simplification of a netlist for an integrated circuit includes steps for generating a variable set representative of the inputs and outputs of logic elements in the netlist, re-ordering the inputs and corresponding outputs of the logic elements in the variable set, generating a key set representative of the inputs of the logic elements that are connected to the outputs, assigning names in the variable set that are representative of equivalent outputs having two or fewer essential variables to the same variable name, inserting names in the variable set representative of outputs having more than two essential variables, and assigning a value to each of the outputs having two or fewer essential variables.
摘要翻译： 一种用于集成电路的网表的全局简化的方法包括以下步骤：产生表示网表中的逻辑元件的输入和输出的变量集，重新排序变量集中的逻辑元素的输入和对应的输出，产生 代表连接到输出的逻辑元件的输入的键集合，将代表具有两个或更少必需变量的等效输出的变量集中的名称分配给相同的变量名称，在代表 具有多于两个基本变量的输出，并且为具有两个或更少必需变量的每个输出分配值。
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公开(公告)号：US06507939B1
公开(公告)日：2003-01-14
申请号：US09858166
申请日：2001-05-15
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： The specification discloses a for reduction of net delays and insertion of buffers in a logic tree having a root and a plurality of leaves. The steps of the method include inserting a plurality of auxiliary nodes into the, defining discrete, approximate scales for delay, load, and ramp time, constructing a set of buffers chains for later insertion into the net tree, determining for each node on the tree a tradeoff function relating ramp time, departure time and load at the node, for each node, removing combinations of the tradeoff functions and the buffer chains, which when inserted into the tradeoff function, lead to a ramp time which exceeds a predetermined maximum allowable ramp time, for each node, using the tradeoff function to determine a minimum delay to insert, and inserting the buffer chain corresponding to the minimum delay as determined by the tradeoff function.
摘要翻译： 该说明书公开了一种用于在具有根和多个叶的逻辑树中减少净延迟和缓冲器的插入。 该方法的步骤包括将多个辅助节点插入到定义离散的近似尺度以用于延迟，加载和斜坡时间，构建一组缓冲器链以供稍后插入到网络树中，确定树上的每个节点 与每个节点相关的斜坡时间，出发时间和节点处的负载的折衷函数，去除折中功能和缓冲链的组合，当组合被插入到权衡函数中时，导致超过预定的最大允许斜坡的斜坡时间 时间，对于每个节点，使用权衡函数来确定插入的最小延迟，以及插入对应于由权衡函数确定的最小延迟的缓冲链。
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公开(公告)号：US07263470B2
公开(公告)日：2007-08-28
申请号：US10429312
申请日：2003-05-05
CPC分类号： G06F17/18
摘要： A Gaussian noise is simulated by discrete analogue ri,j. A first parameter α and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on α, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of α = 2 B - A 2 B and D>i≧0 and 2c>j≧0, where B≧0, 2B>A>0, C≧1 and D≧1, and magnitude s i , j = 1 - α i + α i · 1 - α 2 C · j or s D - 1 , j = 1 - α D - 1 + α D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on α and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.
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14.发明授权Process and apparatus for placement of cells in an IC during floorplan creation 有权在建立平面布置图时，将单元格放置在IC中的过程和装置公开(公告)号：US07036102B2
公开(公告)日：2006-04-25
申请号：US10694208
申请日：2003-10-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are placed in a rectangle and their coordinates of the objects and are adjusted to establish a substantially uniform density of objects in the rectangle. The evaluation of coordinates is performed by placing the wires between cells coordinates and adjusting the cell coordinates to connect the cells to the wires. The substantially uniform density is achieved by dividing the rectangle into first and second rectangles having equal free areas and into third and fourth rectangles having equal areas of objects. The coordinates of the objects are adjusted based on boundaries between the first and second rectangles and between the third and fourth rectangles.
摘要翻译： 将对象放置在矩形中，并且对象的坐标进行调整，以在矩形中建立大致均匀的对象密度。 坐标的评估是通过将电线放在单元之间进行坐标并调整单元坐标来连接单元与导线。 通过将矩形分成具有相等空闲区域的第一和第二矩形以及具有相同面积的物体的第三和第四矩形来实现基本上均匀的密度。 基于第一和第二矩形之间以及第三和第四矩形之间的边界来调整对象的坐标。
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公开(公告)号：US06941494B1
公开(公告)日：2005-09-06
申请号：US10027311
申请日：2001-12-21
CPC分类号： G11C29/26
摘要： A memory test circuit includes a collar for coupling to a memory device for switching an address bus and a data bus of the memory device between an external circuit and the collar in response to a switching signal; and a controller coupled to the collar for generating the switching signal, a test vector, and control signals between the controller and the collar on as few as seven control lines for testing the memory device with the test vector. Multiple memory devices of various sizes may be tested with the same controller concurrently.
摘要翻译： 存储器测试电路包括用于耦合到存储器件的套环，用于响应于切换信号在外部电路和套环之间切换存储器件的地址总线和数据总线; 以及耦合到所述套环的控制器，用于产生所述切换信号，测试向量以及所述控制器和所述套环之间的控制信号，所述控制器和所述套环在多达七个控制线上，用于使用所述测试向量来测试所述存储器 可以同时使用同一控制器测试各种尺寸的多个存储器件。
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16.发明授权Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the same 有权任意块大小的LDPC码的可配置低密度奇偶校验解码器及其配置方法公开(公告)号：US08151160B1
公开(公告)日：2012-04-03
申请号：US12117840
申请日：2008-05-09
IPC分类号： H03M13/00
CPC分类号： H03M13/1117 , H03M13/116 , H03M13/1165 , H03M13/6502 , H03M13/6516 , H03M13/6519 , H03M13/6527 , H03M13/6544
摘要： A configurable low-density parity check code (LDPC) decoder and a method of configuring the decoder. In one embodiment, the configurable LDPC decoder includes: (1) pluralities of parity check units and bit node units, (2) direct and reverse multi-size barrel shifters coupled to the pluralities of parity check units and bit node units and (3) a control circuit, coupled to the pluralities of parity check units and bit node units and the direct and reverse multi-size barrel shifters and configured to configure sizes of the direct and reverse multi-size barrel shifters and numbers of the pluralities of parity check units and bit node units to cooperate therewith based on a block size of a particular LDPC code.
摘要翻译： 一种可配置的低密度奇偶校验码（LDPC）解码器和配置解码器的方法。 在一个实施例中，可配置LDPC解码器包括：（1）多个奇偶校验单元和比特节点单元，（2）耦合到多个奇偶校验单元和比特节点单元的直接和反向多尺寸桶形移位器，以及（3） 耦合到多个奇偶校验单元和比特节点单元的控制电路以及直接和反向多尺寸桶形移位器并且被配置为配置直接和反向多尺寸桶形移位器的大小以及多个奇偶校验单元的数量 以及基于特定LDPC码的块大小来与其配合的比特节点单元。
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公开(公告)号：US07313660B2
公开(公告)日：2007-12-25
申请号：US10656195
申请日：2003-09-04
IPC分类号： G06F12/00
CPC分类号： H04L7/02 , H03M9/00 , Y10T436/143333
摘要： A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number, which establishes a de-serialization level for frequency reduction or phase shifting. An output provides an output data stream at the desired output frequency.
摘要翻译： 频率降低或移相电路具有接收具有输入频率和所需输出频率的表示的输入数据流的输入。 分流器将输入数据流分成多个分离信号，每个信号以期望的输出频率的频率分段。 多个捕获器识别每个相应的分离信号的有效位。 移位器将由至少一些捕获器识别的有效位移位预定数量，其建立用于频率降低或相移的解串级。 输出以期望的输出频率提供输出数据流。
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公开(公告)号：US07062726B2
公开(公告)日：2006-06-13
申请号：US10426549
申请日：2003-04-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library. When the number of elements in the tech-library is at least twice larger than a limit, the number is reduced.
摘要翻译： 本发明涉及一种用于生成用于逻辑功能的技术库的方法。 逻辑函数有很多表示。 对于每个表示，用于实现表示的电路被分解为实例的组合。 实例是通用逻辑电路的分量逻辑电路。 这些实例有预先创建的技术库。 例如，通过基于否定索引对原始物理电路的技术描述进行分类来创建预先创建的技术库。 因此，用于实现表示的电路的技术描述由预先创建的技术库的元素的组合计算。 将每个计算的技术描述与逻辑功能的技术库的每个现有元素进行比较。 当计算出的技术描述至少有一个比逻辑功能的技术库的所有现有元素更好或更小的标记参数时，计算出的技术描述被添加到技术库。 当技术库中的元素数量至少比限制大两倍时，数量就会减少。
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