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公开(公告)号：US06941494B1
公开(公告)日：2005-09-06
申请号：US10027311
申请日：2001-12-21
CPC分类号： G11C29/26
摘要： A memory test circuit includes a collar for coupling to a memory device for switching an address bus and a data bus of the memory device between an external circuit and the collar in response to a switching signal; and a controller coupled to the collar for generating the switching signal, a test vector, and control signals between the controller and the collar on as few as seven control lines for testing the memory device with the test vector. Multiple memory devices of various sizes may be tested with the same controller concurrently.
摘要翻译： 存储器测试电路包括用于耦合到存储器件的套环，用于响应于切换信号在外部电路和套环之间切换存储器件的地址总线和数据总线; 以及耦合到所述套环的控制器，用于产生所述切换信号，测试向量以及所述控制器和所述套环之间的控制信号，所述控制器和所述套环在多达七个控制线上，用于使用所述测试向量来测试所述存储器 可以同时使用同一控制器测试各种尺寸的多个存储器件。
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公开(公告)号：US07050582B1
公开(公告)日：2006-05-23
申请号：US09883733
申请日：2001-06-18
CPC分类号： H04L9/0668
摘要： A method of defining a transformation between an input signal and an output signal. The transformation may implement a pseudo-random one-to-one function that may be implemented in hardware and/or software or modeled in software. The method may comprise the steps of (A) allocating the input signal among a plurality of block input signals, (B) establishing a plurality of transfer functions where each transfer function may be configured to present a plurality of unique symbols as a block output signal responsive to said block input signal, and (C) concatenating the block output signals to form the output signal.
摘要翻译： 一种定义输入信号和输出信号之间变换的方法。 该转换可以实现可以在硬件和/或软件中实现或以软件建模的伪随机一对一功能。 该方法可以包括以下步骤：（A）在多个块输入信号之间分配输入信号，（B）建立多个传递函数，其中每个传递函数可被配置为呈现多个唯一符号作为块输出信号 响应于所述块输入信号，以及（C）串联块输出信号以形成输出信号。
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公开(公告)号：US07822099B2
公开(公告)日：2010-10-26
申请号：US11758975
申请日：2007-06-06
CPC分类号： G06F17/18
摘要： A Gaussian noise is simulated by discrete analogue ri,j. A first parameter α and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on α, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of α = 2 B - A 2 B and D>i≧0 and 2C>j≧0, where B≧0, 2B>A>0, C≧1 and D≧1, and magnitude s i , j = 1 - α i + α i · 1 - α 2 C · j or s D - 1 , j = 1 - α D - 1 + α D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on α and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.
摘要翻译： 高斯噪声由离散模拟ri，j模拟。 选择第一参数α和多个第一和第二整数i和j。 识别多个点i，j，并且基于α，i和j针对每个点计算幅度si，j。 离散的模拟ri，j基于相应的si，j。 给出α= 2 B-A 2 B和D> i≥0和2C>j≥0的实例，其中B≥0,2B> A> 0，C≥1和D≥1，并且幅度si，j = 1-αi +αi·1-α2 C·j·肯·杜·斯D-1，j = 1-αD-1 +αD·1·1 2 C·j。 在一些实施例中，基于α和i定义段。 根据j的相应值将该段划分成点，并且对该段的每个点计算大小。 对于i的每个值迭代地重复定义和分割段并计算幅度。
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公开(公告)号：US07210113B2
公开(公告)日：2007-04-24
申请号：US10830542
申请日：2004-04-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. The coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.
摘要翻译： 通过在模块中创建单元格群，将单元格放置在集成电路平面布置图中，每个簇由连接到模块中的至少一个触发器的路径中的单元或者不连接到任何翻转的路径的单元组成 -flop。 区域在布局图中定义，用于放置模块，并将集群放置在模块中的最佳位置，并将模块放置在区域中的最佳位置。 有选择地重新计算电线，模块和集群的坐标。 群集在平面图中移动以获得更均匀的密度，并且将模块分配给基于模块坐标的区域。
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5.发明授权Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the same 有权任意块大小的LDPC码的可配置低密度奇偶校验解码器及其配置方法公开(公告)号：US08151160B1
公开(公告)日：2012-04-03
申请号：US12117840
申请日：2008-05-09
IPC分类号： H03M13/00
CPC分类号： H03M13/1117 , H03M13/116 , H03M13/1165 , H03M13/6502 , H03M13/6516 , H03M13/6519 , H03M13/6527 , H03M13/6544
摘要： A configurable low-density parity check code (LDPC) decoder and a method of configuring the decoder. In one embodiment, the configurable LDPC decoder includes: (1) pluralities of parity check units and bit node units, (2) direct and reverse multi-size barrel shifters coupled to the pluralities of parity check units and bit node units and (3) a control circuit, coupled to the pluralities of parity check units and bit node units and the direct and reverse multi-size barrel shifters and configured to configure sizes of the direct and reverse multi-size barrel shifters and numbers of the pluralities of parity check units and bit node units to cooperate therewith based on a block size of a particular LDPC code.
摘要翻译： 一种可配置的低密度奇偶校验码（LDPC）解码器和配置解码器的方法。 在一个实施例中，可配置LDPC解码器包括：（1）多个奇偶校验单元和比特节点单元，（2）耦合到多个奇偶校验单元和比特节点单元的直接和反向多尺寸桶形移位器，以及（3） 耦合到多个奇偶校验单元和比特节点单元的控制电路以及直接和反向多尺寸桶形移位器并且被配置为配置直接和反向多尺寸桶形移位器的大小以及多个奇偶校验单元的数量 以及基于特定LDPC码的块大小来与其配合的比特节点单元。
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公开(公告)号：US07313660B2
公开(公告)日：2007-12-25
申请号：US10656195
申请日：2003-09-04
IPC分类号： G06F12/00
CPC分类号： H04L7/02 , H03M9/00 , Y10T436/143333
摘要： A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number, which establishes a de-serialization level for frequency reduction or phase shifting. An output provides an output data stream at the desired output frequency.
摘要翻译： 频率降低或移相电路具有接收具有输入频率和所需输出频率的表示的输入数据流的输入。 分流器将输入数据流分成多个分离信号，每个信号以期望的输出频率的频率分段。 多个捕获器识别每个相应的分离信号的有效位。 移位器将由至少一些捕获器识别的有效位移位预定数量，其建立用于频率降低或相移的解串级。 输出以期望的输出频率提供输出数据流。
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公开(公告)号：US07062726B2
公开(公告)日：2006-06-13
申请号：US10426549
申请日：2003-04-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library. When the number of elements in the tech-library is at least twice larger than a limit, the number is reduced.
摘要翻译： 本发明涉及一种用于生成用于逻辑功能的技术库的方法。 逻辑函数有很多表示。 对于每个表示，用于实现表示的电路被分解为实例的组合。 实例是通用逻辑电路的分量逻辑电路。 这些实例有预先创建的技术库。 例如，通过基于否定索引对原始物理电路的技术描述进行分类来创建预先创建的技术库。 因此，用于实现表示的电路的技术描述由预先创建的技术库的元素的组合计算。 将每个计算的技术描述与逻辑功能的技术库的每个现有元素进行比较。 当计算出的技术描述至少有一个比逻辑功能的技术库的所有现有元素更好或更小的标记参数时，计算出的技术描述被添加到技术库。 当技术库中的元素数量至少比限制大两倍时，数量就会减少。
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公开(公告)号：US07065606B2
公开(公告)日：2006-06-20
申请号：US10655191
申请日：2003-09-04
IPC分类号： G06F12/00
CPC分类号： G06F12/04
摘要： The present invention is directed to a method and apparatus for mapping a customer memory onto a plurality of physical memories. The apparatus may include: (a) a plurality of physical memories onto which a customer memory may be mapped, each of physical memories having a data width of m blocks, the customer memory having a data width of k blocks, and k and m being integers; (b) an address controller, communicatively coupled to a plurality of physical memories, for receiving first address information of the customer memory, for outputting second address information to a plurality of physical memories, and for outputting index information; (c) a data input controller, communicatively coupled to the address controller and a plurality of physical memories, for receiving data of the customer memory and the index information, and for outputting data with a data width of m blocks to a plurality of physical memories; and (d) a data output controller, communicatively coupled to a plurality of physical memories and to the address controller though a delay unit, for receiving the index information, for receiving output, with a width of said m blocks, of a plurality of physical memories, and for outputting the customer memory with a width of said k blocks.
摘要翻译： 本发明涉及一种用于将顾客存储器映射到多个物理存储器上的方法和装置。 该装置可以包括：（a）可以映射客户存储器的多个物理存储器，每个物理存储器具有m个块的数据宽度，该客户存储器的数据宽度为k个块，k和m为 整数 （b）地址控制器，通信地耦合到多个物理存储器，用于接收客户存储器的第一地址信息，用于将第二地址信息输出到多个物理存储器，并用于输出索引信息; （c）数据输入控制器，通信地耦合到地址控制器和多个物理存储器，用于接收客户存储器的数据和索引信息，并且用于将数据宽度为m个块的数据输出到多个物理存储器 ; 以及（d）数据输出控制器，通信地耦合到多个物理存储器，并通过延迟单元与地址控制器通信，用于接收索引信息，用于接收具有所述m个块的宽度的多个物理 存储器，并输出具有所述k个块的宽度的客户存储器。
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公开(公告)号：US06941533B2
公开(公告)日：2005-09-06
申请号：US10277398
申请日：2002-10-21
CPC分类号： G06F17/5077 , G06F1/10 , G06F17/5045 , G06F2217/62
摘要： A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells, partitioning the set of memory cells into segments, constructing a first clock tree having a first root vertex with a corresponding initial skew for each of the segments, constructing a second clock tree having a second root vertex with a corresponding initial skew for the set of non-memory cells, delay balancing the first root vertex and the second vertex clock tree, and inserting a clock buffer at a midpoint between the first root vertex and the second root vertex.
摘要翻译： 一种合成用于降低集成电路设计中的峰值功率的时钟树的方法包括将电路设计划分成一组存储器单元和一组非存储器单元，将该组存储器单元分成段，构建第一时钟树 具有对于每个段具有对应的初始偏移的第一根顶点，构造具有第二根顶点的第二时钟树，该第二根顶点具有用于所述非存储器单元组的对应的初始偏移，延迟平衡所述第一根顶点和所述第二顶点 时钟树，并且在第一根顶点和第二根顶点之间的中点处插入时钟缓冲器。
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公开(公告)号：US06848094B2
公开(公告)日：2005-01-25
申请号：US10334731
申请日：2002-12-31
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method of global simplification of a netlist for an integrated circuit includes steps for generating a variable set representative of the inputs and outputs of logic elements in the netlist, re-ordering the inputs and corresponding outputs of the logic elements in the variable set, generating a key set representative of the inputs of the logic elements that are connected to the outputs, assigning names in the variable set that are representative of equivalent outputs having two or fewer essential variables to the same variable name, inserting names in the variable set representative of outputs having more than two essential variables, and assigning a value to each of the outputs having two or fewer essential variables.
摘要翻译： 一种用于集成电路的网表的全局简化的方法包括以下步骤：产生表示网表中的逻辑元件的输入和输出的变量集，重新排序变量集中的逻辑元素的输入和对应的输出，产生 代表连接到输出的逻辑元件的输入的键集合，将代表具有两个或更少必需变量的等效输出的变量集中的名称分配给相同的变量名称，在代表 具有多于两个基本变量的输出，并且为具有两个或更少必需变量的每个输出分配值。
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