公开(公告)号：US08224614B2

公开(公告)日：2012-07-17

申请号：US12609022

申请日：2009-10-30

申请人： Allon Adir ,  Maxim Golubev ,  Andrey Klinger ,  Amir Nahir

发明人： Allon Adir ,  Maxim Golubev ,  Andrey Klinger ,  Amir Nahir

IPC分类号： G01R31/00 ,  G06F19/00

CPC分类号： G01R31/318314 ,  G06F11/2236

摘要： A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in sequential order, concurrently, a combination thereof or the like. The first test template may be configured to be executed by a single-core machine and may be transformed to a multi-core test template that is configured to be executed on a multi-core machine in parallel to other tests. By utilizing the disclosed subject matter, a reduction in overhead of executing the first and second test templates may be achieved; a predetermined interleaving may be performed and a user may control the manner in which the combination test template is executing the first and second test templates. Additionally, reuse of pre-silicon test templates in post-silicon stage may be achieved.

摘要翻译： 将第一和第二测试模板组合到组合测试模板。 组合测试模板可以被配置为组合地执行第一和第二测试模板，并且基于定义。 组合测试模板可以按顺序执行测试，同时，其组合等。 第一测试模板可以被配置为由单核机器执行，并且可以被转换成被配置为在多核机器上并行执行的多核测试模板。 通过利用所公开的主题，可以实现执行第一和第二测试模板的开销的减少; 可以执行预定的交织，并且用户可以控制组合测试模板正在执行第一和第二测试模板的方式。 此外，可以实现硅后测试模板在硅后期的再利用。

公开(公告)号：US20120054560A1

公开(公告)日：2012-03-01

申请号：US12843068

申请日：2010-08-26

申请人： Allon Adir ,  John Martin Ludden ,  Avi Ziv

发明人： Allon Adir ,  John Martin Ludden ,  Avi Ziv

IPC分类号： G06F11/00 ,  G06F9/45

CPC分类号： G06F17/5022 ,  G06F11/3664 ,  G06F2217/68

摘要： An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.

摘要翻译： 通过模拟测试程序的执行和更新交易顺序图以识别周期来检查处理器相对于交易的操作。 基于在第一事务的执行期间读取的值和被配置为设置具有读取值的存储器的第二事务来更新该图。 该测试程序包括用于识别第二个事务的信息。

公开(公告)号：US07945888B2

公开(公告)日：2011-05-17

申请号：US12038818

申请日：2008-02-28

申请人： Allon Adir ,  Gil Eliezer Shurek

发明人： Allon Adir ,  Gil Eliezer Shurek

IPC分类号： G06F17/50 ,  G06F9/44 ,  G06F9/455 ,  G06F11/22

CPC分类号： G06F11/261 ,  G06F17/5022

摘要： Device, system and method for verification of a hardware system-under-test including at least one processor. A method includes building an executable image of a hardware exerciser adapted for execution on a test platform selected from: a simulation accelerator, a hardware emulator, a prototype hardware system, and a hardware production wafer. The exerciser image includes embedded data corresponding to architectural knowledge, testing knowledge, and a test template. The test template is defined in a context-free formal language and includes biasing directives to influence at least one of a desired test structure, one or more resources to be included in the test, and one or more values of the included resources. The architectural knowledge is obtained from an architectural model including a formal description of the specification for the system-under-test, and the testing knowledge is obtained from a testing knowledgebase including heuristics for testing desired aspects of the system-under-test.

摘要翻译： 用于验证包括至少一个处理器的被测硬件系统的设备，系统和方法。 一种方法包括构建适于在选自以下的测试平台上执行的硬件训练器的可执行映像：模拟加速器，硬件仿真器，原型硬件系统和硬件生产晶片。 训练者图像包括对应于建筑知识，测试知识和测试模板的嵌入数据。 测试模板以无上下文的形式语言定义，并且包括偏好指令以影响期望的测试结构，要包括在测试中的一个或多个资源中的至少一个以及所包括的资源的一个或多个值。 建筑知识是从建筑模型中获得的，包括对被测系统的规范的正式描述，并且测试知识从测试知识库获得，包括用于测试被测系统的期望方面的启发式。

公开(公告)号：US20100082719A1

公开(公告)日：2010-04-01

申请号：US12239783

申请日：2008-09-28

申请人： Allon Adir ,  Ehud Aharoni ,  Oded Margalit

发明人： Allon Adir ,  Ehud Aharoni ,  Oded Margalit

IPC分类号： G06F7/58

CPC分类号： G06F7/582 ,  G06F7/586

摘要： Generating a number based on a bitset constraints. For example, a method of generating a pseudo random number satisfying a bitset constraint may include determining a number of possible solutions satisfying the bitset constraint; selecting an index representing a solution of the possible solutions; and generating the pseudo-random number based on the index. Other embodiments are described and claimed.

摘要翻译： 基于一个位组约束生成一个数字。 例如，产生满足比特组约束的伪随机数的方法可以包括确定满足比特组约束的可能解的数量; 选择表示可能解决方案的解的索引; 以及基于所述索引生成所述伪随机数。 描述和要求保护其他实施例。

公开(公告)号：US07571201B1

公开(公告)日：2009-08-04

申请号：US12061808

申请日：2008-04-03

申请人： Allon Adir ,  Gil E. Shurek

发明人： Allon Adir ,  Gil E. Shurek

IPC分类号： G06F1/02

CPC分类号： G06F9/52

摘要： A method for making joint pseudo random decisions in a distributed program comprises providing a common original seed value to a plurality of processes in the distributed program, generating the same sequence of pseudo random numbers for each of said plurality of processes using the common original seed, and using pseudo random numbers in the sequence to make successive joint pseudo random decisions. If a process has to make a pseudo random decision that is not joint, it uses another seed or method.

摘要翻译： 一种用于在分布式程序中进行联合伪随机决策的方法包括：向所述分布式程序中的多个进程提供公共原始种子值，使用所述共同原始种子为所述多个进程中的每一个生成相同的伪随机数序列， 并在序列中使用伪随机数来进行连续的联合伪随机决策。 如果进程必须进行不联合的伪随机决策，则它将使用另一个种子或方法。

公开(公告)号：US07370296B2

公开(公告)日：2008-05-06

申请号：US10853041

申请日：2004-05-25

申请人： Anatoly Koyfman ,  Allon Adir ,  Roy Emek ,  Yoav Katz ,  Michael Vinov

发明人： Anatoly Koyfman ,  Allon Adir ,  Roy Emek ,  Yoav Katz ,  Michael Vinov

IPC分类号： G06F17/50

CPC分类号： G06F11/263 ,  G06F11/2257

摘要： Methods and systems are disclosed that enhance the ability of a test generator to automatically deal with address translation in a processor design, and without need for creating specific code. A model of the address translation mechanism of a design-under-test is represented as a directed acyclic graph and then converted into a constraint satisfaction problem. The problem is solved by a CSP engine, and the solution used to generate test cases for execution. Using the model, testing knowledge can be propagated to models applicable to many different designs to produce extensive coverage of address translation mechanisms.

摘要翻译： 公开了增强测试发生器在处理器设计中自动处理地址转换并且不需要创建特定代码的能力的方法和系统。 被测设计的地址转换机制的模型被表示为有向非循环图，然后转换成约束满足问题。 这个问题由CSP引擎解决，用于生成用于执行的测试用例的解决方案。 使用该模型，测试知识可以传播到适用于许多不同设计的模型，以产生广泛的地址转换机制。

公开(公告)号：US20060184468A1

公开(公告)日：2006-08-17

申请号：US11040241

申请日：2005-01-21

申请人： Allon Adir ,  Eyal Bin ,  Roy Emek ,  Kirill Shoikhet

发明人： Allon Adir ,  Eyal Bin ,  Roy Emek ,  Kirill Shoikhet

IPC分类号： G06F15/18

CPC分类号： G06F11/3684

摘要： A method for automatically generating test programs includes receiving a description of a system under test, expressed in terms of variables associated with the system and conditional constraints including semantics applied to the variables, and receiving a definition of an event to be tested in the system. The method generates an ECondCSP over the variables responsively to the definition of the event and to the conditional constraints, such that at least some of the semantics of the conditional constraints are preserved in the ECondCSP when one or more of the variables to which the semantics are applied are inactive. The ECondCSP is solved to generate a test case for the system.

摘要翻译： 一种用于自动生成测试程序的方法包括：接收对与系统相关的变量表示的被测系统的描述，以及包括应用于变量的语义的条件约束，以及接收系统中要测试的事件的定义。 该方法响应于事件的定义和条件约束而对变量生成ECondCSP，使得条件约束的至少一些语义在ECondCSP中被保留，当一个或多个语义为 应用不活动。 ECondCSP解决了为系统生成测试用例。

公开(公告)号：US20050278702A1

公开(公告)日：2005-12-15

申请号：US10853041

申请日：2004-05-25

申请人： Anatoly Koyfman ,  Allon Adir ,  Roy Emek ,  Yoav Katz ,  Michael Vinov

发明人： Anatoly Koyfman ,  Allon Adir ,  Roy Emek ,  Yoav Katz ,  Michael Vinov

IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F11/00 ,  G06F11/25 ,  G06F11/263 ,  G06F17/50 ,  G06K5/04

CPC分类号： G06F11/263 ,  G06F11/2257

摘要： Methods and systems are disclosed that enhance the ability of a test generator to automatically deal with address translation in a processor design, and without need for creating specific code. A model of the address translation mechanism of a design-under-test is represented as a directed acyclic graph and then converted into a constraint satisfaction problem. The problem is solved by a CSP engine, and the solution used to generate test cases for execution. Using the model, testing knowledge can be propagated to models applicable to many different designs to produce extensive coverage of address translation mechanisms.

摘要翻译： 公开了增强测试发生器在处理器设计中自动处理地址转换并且不需要创建特定代码的能力的方法和系统。 被测设计的地址转换机制的模型被表示为有向非循环图，然后转换成约束满足问题。 这个问题由CSP引擎解决，用于生成用于执行的测试用例的解决方案。 使用该模型，测试知识可以传播到适用于许多不同设计的模型，以产生广泛的地址转换机制。

公开(公告)号：US09886369B2

公开(公告)日：2018-02-06

申请号：US13295070

申请日：2011-11-13

申请人： Allon Adir ,  Ronen Levy ,  Tamer Salman

发明人： Allon Adir ,  Ronen Levy ,  Tamer Salman

IPC分类号： G06F11/36

CPC分类号： G06F11/3684

摘要： A computer-implemented method and apparatus for fabricating data for database applications. The method comprises intercepting a command issued by an application, the command being addressed to a database; formulating a problem in accordance with the command; obtaining a solution for the problem, the solution comprising fabricated data; providing a second command for updating the database with the fabricated data; and providing the command to the database, whereby a response from the database based on the fabricated data is provided to the application.

公开(公告)号：US08806270B2

公开(公告)日：2014-08-12

申请号：US13295104

申请日：2011-11-14

申请人： Allon Adir ,  Dimtry Krestyashyn ,  Charles Meissner ,  Amir Nahir

发明人： Allon Adir ,  Dimtry Krestyashyn ,  Charles Meissner ,  Amir Nahir

IPC分类号： G06F11/00

CPC分类号： G06F11/3612

摘要： A computer-implemented method and apparatus, comprising: having a plurality of processing entities operating substantially concurrently in a computerized platform enabling transaction operations, wherein the plurality of processing entities comprise two or more entities adapted to store values, and one or more entity adapted to load values, wherein each writing entity is associated with a private memory location within a memory unit; storing symbols into an associated target memory location by each of the entities adapted to store values, wherein symbols are stored according to a predetermined order, wherein a symbol is stored using a transaction; loading a multiplicity of private memory locations by the at least one entity adapted to load values, to obtain loaded values; and analyzing the loaded values for at least one invariant.

摘要翻译： 一种计算机实现的方法和装置，包括：具有多个处理实体，所述多个处理实体在计算机化平台中基本同时运行，从而实现事务操作，其中所述多个处理实体包括适于存储值的两个或多个实体，以及适于 负载值，其中每个写入实体与存储器单元内的专用存储器位置相关联; 通过适于存储值的每个实体将符号存储到相关联的目标存储器位置，其中符号根据预定顺序存储，其中使用事务存储符号; 通过适于加载值的至少一个实体加载多个私有存储器位置，以获得加载的值; 并分析至少一个不变量的加载值。