公开(公告)号：US20110208945A1

公开(公告)日：2011-08-25

申请号：US12709533

申请日：2010-02-22

申请人： Allon Adir ,  Gil Shurek

发明人： Allon Adir ,  Gil Shurek

IPC分类号： G06F12/00

CPC分类号： G06F12/1425

摘要： Testing a circuit in a post-silicon stage is performed by enabling the different processing entities of the circuit to determine a consistent access permissions schema in a random manner. Based upon the consistent access permissions schema, addresses to be accessed during the testing of the circuit may be determined. The addresses may be determined in a random manner. The consistent permissions schema may be determined based on a template representative of repetitive portions of access permissions schema. The disclosed subject matter may utilize biasing modules to bias the test generation to provide a test having a predetermined characteristic. The disclosed subject matter may utilize a joint random seed or other techniques to provide for consistent random decisions by the different processing entities.

摘要翻译： 通过使电路的不同处理实体以随机方式确定一致的访问许可模式来执行后硅阶段中的电路测试。 基于一致的访问许可模式，可以确定在电路测试期间要访问的地址。 地址可以以随机方式确定。 可以基于表示访问许可模式的重复部分的模板来确定一致的权限模式。 所公开的主题可以利用偏置模块来偏置测试生成以提供具有预定特性的测试。 所公开的主题可以利用联合随机种子或其他技术来提供不同处理实体的一致随机决定。

公开(公告)号：US20110197049A1

公开(公告)日：2011-08-11

申请号：US12700970

申请日：2010-02-05

申请人： Allon Adir ,  Brad Lee Herold ,  John Martin Ludden ,  Pedro Martin-de-Nicolas ,  Charles Leverett Meissner ,  Gil Eliezer Shurek

发明人： Allon Adir ,  Brad Lee Herold ,  John Martin Ludden ,  Pedro Martin-de-Nicolas ,  Charles Leverett Meissner ,  Gil Eliezer Shurek

IPC分类号： G06F9/38

CPC分类号： G06F9/3816 ,  G06F9/3005

摘要： A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the redirection instruction with a replacement instruction having a desired result resolved in accordance with the current machine state. The instructions that are replaced may be conditional branch instructions and the result a desired execution path. The examination of the machine state permits determination of a branch condition for the replacement instruction so that the next pass of the test code executes along the desired path. Alternatively, the handler can execute a jump to the branch instruction, causing immediate execution of the desired branch path. The re-direction instructions may be illegal instructions, which cause execution of an interrupt handler that performs the replacement.

摘要翻译： 使用特殊重定向指令替代具有机器状态相关结果的指令的测试代码生成技术提供测试代码的生成，其中在不使用状态模型的情况下进行状态相关的执行选择。 重定向指令导致处理程序的执行，而不是检查机器状态，并根据当前机器状态用具有期望结果的替换指令替换重定向指令。 被替换的指令可以是条件分支指令，并且结果是可能的执行路径。 对机器状态的检查允许确定替换指令的分支条件，使得测试代码的下一遍沿着期望的路径执行。 或者，处理程序可以执行跳转到分支指令，导致立即执行所需的分支路径。 重定向指令可能是非法指令，这些指令导致执行替换的中断处理程序的执行。

公开(公告)号：US06925405B2

公开(公告)日：2005-08-02

申请号：US10040940

申请日：2002-01-09

申请人： Allon Adir ,  Roy Emek ,  Eitan Marcus

发明人： Allon Adir ,  Roy Emek ,  Eitan Marcus

IPC分类号： G01R27/28 ,  G06F11/263 ,  G06F19/00

CPC分类号： G06F11/263

摘要： A test program generator that produces test instructions according to a specification of a system being verified. The instructions are typically generated randomly, at least in part, and are then. The system is capable of interpreting events, detecting an impending occurrence of an event, and responding to the event by switching to an alternate input stream.

摘要翻译： 一种测试程序生成器，其根据被验证的系统的规范产生测试指令。 指令通常随机生成，至少部分地，然后是。 该系统能够解释事件，检测即将发生的事件，以及通过切换到替代输入流来响应事件。

公开(公告)号：US09886369B2

公开(公告)日：2018-02-06

申请号：US13295070

申请日：2011-11-13

申请人： Allon Adir ,  Ronen Levy ,  Tamer Salman

发明人： Allon Adir ,  Ronen Levy ,  Tamer Salman

IPC分类号： G06F11/36

CPC分类号： G06F11/3684

摘要： A computer-implemented method and apparatus for fabricating data for database applications. The method comprises intercepting a command issued by an application, the command being addressed to a database; formulating a problem in accordance with the command; obtaining a solution for the problem, the solution comprising fabricated data; providing a second command for updating the database with the fabricated data; and providing the command to the database, whereby a response from the database based on the fabricated data is provided to the application.

公开(公告)号：US08806270B2

公开(公告)日：2014-08-12

申请号：US13295104

申请日：2011-11-14

申请人： Allon Adir ,  Dimtry Krestyashyn ,  Charles Meissner ,  Amir Nahir

发明人： Allon Adir ,  Dimtry Krestyashyn ,  Charles Meissner ,  Amir Nahir

IPC分类号： G06F11/00

CPC分类号： G06F11/3612

摘要： A computer-implemented method and apparatus, comprising: having a plurality of processing entities operating substantially concurrently in a computerized platform enabling transaction operations, wherein the plurality of processing entities comprise two or more entities adapted to store values, and one or more entity adapted to load values, wherein each writing entity is associated with a private memory location within a memory unit; storing symbols into an associated target memory location by each of the entities adapted to store values, wherein symbols are stored according to a predetermined order, wherein a symbol is stored using a transaction; loading a multiplicity of private memory locations by the at least one entity adapted to load values, to obtain loaded values; and analyzing the loaded values for at least one invariant.

摘要翻译： 一种计算机实现的方法和装置，包括：具有多个处理实体，所述多个处理实体在计算机化平台中基本同时运行，从而实现事务操作，其中所述多个处理实体包括适于存储值的两个或多个实体，以及适于 负载值，其中每个写入实体与存储器单元内的专用存储器位置相关联; 通过适于存储值的每个实体将符号存储到相关联的目标存储器位置，其中符号根据预定顺序存储，其中使用事务存储符号; 通过适于加载值的至少一个实体加载多个私有存储器位置，以获得加载的值; 并分析至少一个不变量的加载值。

公开(公告)号：US08589734B2

公开(公告)日：2013-11-19

申请号：US12843068

申请日：2010-08-26

申请人： Allon Adir ,  John Martin Ludden ,  Avi Ziv

发明人： Allon Adir ,  John Martin Ludden ,  Avi Ziv

IPC分类号： G06F11/00

CPC分类号： G06F17/5022 ,  G06F11/3664 ,  G06F2217/68

摘要： An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.

摘要翻译： 通过模拟测试程序的执行和更新交易顺序图以识别周期来检查处理器相对于交易的操作。 基于在第一事务的执行期间读取的值和被配置为设置具有读取值的存储器的第二事务来更新该图。 该测试程序包括用于识别第二个事务的信息。

公开(公告)号：US08412507B2

公开(公告)日：2013-04-02

申请号：US11947100

申请日：2007-11-29

申请人： Allon Adir ,  Sigal Asaf

发明人： Allon Adir ,  Sigal Asaf

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method for compliance testing of a circuit design that includes at least one processor and a memory includes defining a memory model. The memory model includes synchronization mechanisms for synchronizing access to the memory by software instructions in different program threads running on the at least one processor. Synchronization-related parameters, which are applicable to at least one sequence of the software instructions in the different program threads, are specified. A coverage model is defined as a multi-dimensional cross-product of values of the synchronization-related parameters. At least one test program is generated using the coverage model, and a compliance of the design with the memory model is tested by subjecting the design to the at least one test program.

摘要翻译： 包括至少一个处理器和存储器的电路设计的符合性测试的方法包括定义存储器模型。 存储器模型包括用于通过在至少一个处理器上运行的不同程序线程中的软件指令来同步对存储器的访问的同步机制。 指定适用于不同程序线程中的软件指令的至少一个序列的同步相关参数。 覆盖模型被定义为同步相关参数值的多维交叉积。 使用覆盖模型生成至少一个测试程序，并且通过对设计进行至少一个测试程序来测试设计与存储器模型的一致性。

公开(公告)号：US20130013246A1

公开(公告)日：2013-01-10

申请号：US13179526

申请日：2011-07-10

申请人： Allon Adir ,  Eyal Bin ,  Shady Copty ,  Anatoly Koyfman ,  Shimon Landa ,  Amir Nahir ,  Vitali Sokhin ,  Elena Tsanko

发明人： Allon Adir ,  Eyal Bin ,  Shady Copty ,  Anatoly Koyfman ,  Shimon Landa ,  Amir Nahir ,  Vitali Sokhin ,  Elena Tsanko

IPC分类号： H01L21/66 ,  G06F19/00

CPC分类号： G06F11/263

摘要： An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection.

摘要翻译： 一种由计算机化设备执行的装置和计算机实现的方法，包括：生成用于测试一个或多个域的测试数据的集合，其中所述测试数据对于硬件设备的后硅验证是有用的; 根据要测试的硬件设备选择测试数据的集合的子集，以及相对于硬件设备测试的至少一个域; 并索引测试数据集合的子集以获得索引集合。

公开(公告)号：US08055492B2

公开(公告)日：2011-11-08

申请号：US10041671

申请日：2002-01-10

申请人： Allon Adir

发明人： Allon Adir

IPC分类号： G06F17/50 ,  G06F9/44 ,  G06F11/22 ,  G06F13/00 ,  G01N31/00

CPC分类号： G01R31/318357 ,  G06F17/5022

摘要： A design verification system that verifies the operation of multi-processor architecture by generating test programs in which the behavior of the processor, when executing the test program, is evaluated against the behavior required by the design specification. The test program generator produces scenarios for a multi-processor design in which non-unique results may occur. The system is provided with facilities to report expected outcomes, and to evaluate the validity of non-unique results in multiple resources under conditions of non-unique result propagation and dependencies among adjacent and non-adjacent resources.

摘要翻译： 一种设计验证系统，其通过生成测试程序来验证多处理器架构的操作，其中在执行测试程序时处理器的行为被针对设计规范所要求的行为进行评估。 测试程序生成器生成多处理器设计的场景，其中可能发生非唯一的结果。 该系统提供了报告预期结果的设施，并且在非唯一结果传播和相邻资源与非相邻资源之间的依赖性条件下，在多种资源中评估非唯一结果的有效性。

公开(公告)号：US20090222694A1

公开(公告)日：2009-09-03

申请号：US12038818

申请日：2008-02-28

申请人： Allon Adir ,  Gil Eliezer Shurek

发明人： Allon Adir ,  Gil Eliezer Shurek

IPC分类号： G06F11/00

CPC分类号： G06F11/261 ,  G06F17/5022

摘要： Device, system and method for verification of a hardware system-under-test including at least one processor. A method includes building an executable image of a hardware exerciser adapted for execution on a test platform selected from: a simulation accelerator, a hardware emulator, a prototype hardware system, and a hardware production wafer. The exerciser image includes embedded data corresponding to architectural knowledge, testing knowledge, and a test template. The test template is defined in a context-free formal language and includes biasing directives to influence at least one of a desired test structure, one or more resources to be included in the test, and one or more values of the included resources. The architectural knowledge is obtained from an architectural model including a formal description of the specification for the system-under-test, and the testing knowledge is obtained from a testing knowledgebase including heuristics for testing desired aspects of the system-under-test.

摘要翻译： 用于验证包括至少一个处理器的被测硬件系统的设备，系统和方法。 一种方法包括构建适于在选自以下的测试平台上执行的硬件训练器的可执行映像：模拟加速器，硬件仿真器，原型硬件系统和硬件生产晶片。 训练者图像包括对应于建筑知识，测试知识和测试模板的嵌入数据。 测试模板以无上下文的形式语言定义，并且包括偏好指令以影响期望的测试结构，要包括在测试中的一个或多个资源中的至少一个以及所包括的资源的一个或多个值。 建筑知识是从建筑模型中获得的，包括对被测系统的规范的正式描述，并且测试知识从测试知识库获得，包括用于测试待测系统的期望方面的启发式。