公开(公告)号：US10746792B1

公开(公告)日：2020-08-18

申请号：US16206761

申请日：2018-11-30

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Gil Stoler ,  Nafea Bshara

IPC: G01R31/28 ,  G01R31/317 ,  G06N20/00

Abstract: An error-handling processing circuit and system are provided. The system can receive an error signal, such as an interrupt, and decouple (e.g., by a gate signal) a functional clock from a processing block, in some instances effectively halting the processing block's operation. This can prevent a cascade of interdependent errors, thereby avoiding producing redundant or confusing error information. The system can include the processing block, a debug clock not coupled to the processing block, and a data block (e.g., a register file) coupled to the debug clock and to an external input/output interface. The data block can be configured to continue receiving a clock signal via a multiplexer from the debug clock without disruption after the functional clock is decoupled, enabling the data block to remain operational for debugging.

公开(公告)号：US09411731B2

公开(公告)日：2016-08-09

申请号：US14829410

申请日：2015-08-18

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/08 ,  G11C7/10

CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.