公开(公告)号：US07403039B1

公开(公告)日：2008-07-22

申请号：US11670537

申请日：2007-02-02

申请人： Igor Arsovski ,  Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

发明人： Igor Arsovski ,  Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

IPC分类号： H03K19/0175

CPC分类号： H03K19/018585 ,  H03K3/35613 ,  H03K5/133 ,  H03K2005/00058 ,  H03K2005/00208 ,  H03K2005/00228

摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.

公开(公告)号：US08016482B2

公开(公告)日：2011-09-13

申请号：US11780530

申请日：2007-07-20

申请人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iandanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

发明人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iandanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

IPC分类号： G01K7/01 ,  G01K17/00 ,  G01N25/00

CPC分类号： G05D23/20 ,  G05D23/1934

摘要： Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

摘要翻译： 公开了对集成电路（IC）供电的方法和系统。 在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热， 以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

公开(公告)号：US07053712B2

公开(公告)日：2006-05-30

申请号：US10710745

申请日：2004-07-30

申请人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Michael A. Sorna ,  Sebastian T. Ventrone

发明人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Michael A. Sorna ,  Sebastian T. Ventrone

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/4565 ,  H03F3/45659 ,  H03F2200/78 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45521

摘要： A method for controlling the common-mode output voltage in a fully differential amplifier includes comparing a sensed common-mode output voltage of the fully differential amplifier to a reference voltage, and generating an error signal representing the difference between the sensed common-mode output voltage and the reference voltage. The error signal is utilized to control the body voltage of one or more FET devices included within the fully differential amplifier until the sensed common-mode output voltage is in agreement with said reference voltage.

摘要翻译： 一种用于控制全差分放大器中的共模输出电压的方法包括将全差分放大器的感测共模输出电压与参考电压进行比较，并产生一个误差信号，该误差信号表示检测到的共模输出电压 和参考电压。 误差信号用于控制包括在全差分放大器内的一个或多个FET器件的体电压，直到检测到的共模输出电压与所述参考电压一致。

公开(公告)号：US07501880B2

公开(公告)日：2009-03-10

申请号：US10906628

申请日：2005-02-28

申请人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr.

发明人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr.

IPC分类号： G05F1/10

CPC分类号： G05F3/262

摘要： A body-biased enhanced current mirror circuit is disclosed wherein the body voltage of a current mirror device is adjusted to compensate for the effect of changes in the output voltage on the output current, increasing the output impedance. For each instance of the current mirror, this approach has the advantage of requiring no additional margin in operating voltage and of consuming no more circuit area than prior art current mirror designs. In addition, the body-biased enhanced current mirror circuit provides a stable reference current to output current ratio over a wide operating range. An auxiliary MOSFET current mirror device with the body connected to ground may be added in parallel with the body-biased current mirror device to eliminate a non-monotonicity of the current output.

摘要翻译： 公开了体偏置增强电流镜电路，其中调整电流镜装置的体电压以补偿输出电压对输出电流的变化的影响，增加输出阻抗。 对于电流镜的每个实例，这种方法的优点在于不需要额外的工作电压余量，并且消耗的电路面积比现有技术的电流镜设计更多。 此外，体偏置增强电流镜电路在宽的工作范围内提供稳定的参考电流至输出电流比。 可以将主体连接到地的辅助MOSFET电流镜装置与主体偏置电流镜装置并联，以消除电流输出的非单调性。

公开(公告)号：US07479819B2

公开(公告)日：2009-01-20

申请号：US11610848

申请日：2006-12-14

申请人： Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

发明人： Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

公开(公告)号：US07404114B2

公开(公告)日：2008-07-22

申请号：US10906343

申请日：2005-02-15

申请人： Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

发明人： Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

IPC分类号： G01R31/28

CPC分类号： H03K5/133 ,  H03K2005/00032

摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

摘要翻译： 在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。 通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。 将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压 在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

公开(公告)号：US06298458B1

公开(公告)日：2001-10-02

申请号：US09225111

申请日：1999-01-04

申请人： Hayden C. Cranford, Jr. ,  Eirik Gude ,  Joseph A. Iadanza ,  Paul A. Owczarski ,  Jonathan H. Raymond

发明人： Hayden C. Cranford, Jr. ,  Eirik Gude ,  Joseph A. Iadanza ,  Paul A. Owczarski ,  Jonathan H. Raymond

IPC分类号： G01R3128

CPC分类号： H04L43/50 ,  G01R31/2884 ,  H04B17/10 ,  H04B17/20

摘要： A system and method for testing the most complex portions of transceiver devices integrated into digital VLSI chips. The testing is performed in a manufacturing environment with minimal external hardware and using a combination of test-specific circuitry and pattern algorithms built into a mixed signal transceiver implementing a test methodology suitable for application and measurement on a digital tester.

摘要翻译： 用于测试集成到数字VLSI芯片中的收发器设备的最复杂部分的系统和方法。 该测试在具有最小外部硬件的制造环境中进行，并且使用内置于混合信号收发器中的测试专用电路和模式算法的组合来实现适用于数字测试仪上的应用和测量的测试方法。

公开(公告)号：US07898286B2

公开(公告)日：2011-03-01

申请号：US12369066

申请日：2009-02-11

申请人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

发明人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

IPC分类号： H03K19/00

CPC分类号： G01R31/31725

摘要： Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.

摘要翻译： 用于管芯或芯片的跨管芯连接结构和方法包括具有缓冲器驱动器和旁路的缓冲器元件以及耦合到缓冲器元件的控制线，以便为每个相应的缓冲元件选择缓冲器驱动器和旁路中的一个。 逻辑网络被布置成具有缓冲元件以形成功能路径，测试单元被构造和布置以测试功能路径并耦合到控制线，以及配置存储寄存器，用于设置所选缓冲器驱动器和 绕过每个通过的功能路径。

公开(公告)号：US07218135B2

公开(公告)日：2007-05-15

申请号：US11163015

申请日：2005-09-30

申请人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

发明人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone

IPC分类号： H03K19/003 ,  H03K17/16

CPC分类号： H03K19/00346

摘要： An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

摘要翻译： 集成电路设备包括功能逻辑，抗噪声机器和状态监测点，其为抗噪声机器提供与用于监视功能逻辑状态的功能逻辑的接口。 抗噪声机器包括定义用于功能逻辑的噪声前导状态的标记，以及耦合到状态监测点的识别逻辑。 抗噪声机器可操作以响应于与标记匹配的功能逻辑噪声前导状态中的识别逻辑检测产生抗噪声。

公开(公告)号：US07511548B2

公开(公告)日：2009-03-31

申请号：US11610963

申请日：2006-12-14

申请人： Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

发明人： Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

IPC分类号： G06F1/04

CPC分类号： G06F17/5045 ,  G06F2217/62

摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

摘要翻译： 公开了一种用于提供平衡负载的时钟分配网络，结构和方法。 特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。 每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。 此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。