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    COMPRESSED SCAN TESTING TECHNIQUES
    11.
    发明申请
    COMPRESSED SCAN TESTING TECHNIQUES 有权
    压缩扫描测试技术

    公开(公告)号：US20160091564A1

    公开(公告)日：2016-03-31

    申请号：US14502284

    申请日：2014-09-30

    Applicant: Apple Inc.

    Inventor： Bibo Li ,  Andrew J. Copperhall ,  Bo Yang

    IPC: G01R31/3177

    CPC classification number: G01R31/318566 ,  G01R31/318544

    Abstract: Techniques are disclosed relating to test equipment. In one embodiment, a method includes receiving failure information from a first test of a device under test (DUT). In this embodiment, the DUT includes a plurality of scan chains that each include a plurality of scan cells. In this embodiment, the first test is based on a first compressed test pattern. In this embodiment, the failure information does not permit a definitive determination as to which scan cell is a failing scan cell. In this embodiment, the method includes generating a plurality of compressed test patterns based on the first compressed test pattern. In this embodiment, the plurality of compressed test patterns specify one-to-one-modes. In this embodiment, the method includes performing one or more second tests of the DUT using the plurality of compressed test patterns to definitively determine one or more failing scan cells.

    Abstract translation: 公开了与测试设备有关的技术。 在一个实施例中，一种方法包括从被测设备（DUT）的第一测试接收故障信息。 在该实施例中，DUT包括多个扫描链，每条扫描链包括多个扫描单元。 在该实施例中，第一测试基于第一压缩测试图案。 在本实施例中，故障信息不能确定哪个扫描单元是故障扫描单元。 在该实施例中，该方法包括基于第一压缩测试图案生成多个压缩测试图案。 在该实施例中，多个压缩测试图案指定一对一模式。 在该实施例中，该方法包括使用多个压缩测试模式来执行DUT的一个或多个第二测试，以确定确定一个或多个故障扫描单元。

    Scan Data Transfer Circuits for Multi-die Chip Testing
    12.
    发明申请
    Scan Data Transfer Circuits for Multi-die Chip Testing 有权

    公开(公告)号：US20250093416A1

    公开(公告)日：2025-03-20

    申请号：US18391145

    申请日：2023-12-20

    Applicant: Apple Inc.

    Inventor： Bo Yang ,  Heon C. Kim ,  Vasu P. Ganti

    IPC: G01R31/3185 ,  G01R31/317

    Abstract: An apparatus includes a first set of scan-enabled flip-flop circuits may be configured to shift a scan-chain pattern from a first test input node to a first test output node using a first clock signal. A particular lockup latch may be coupled to the first test output node and to a second test input node. This particular lockup latch may be configured to, when enabled, delay propagation of the scan-chain pattern from the first test output node to the second test input node. A second set of scan-enabled flip-flop circuits may be configured to shift the scan-chain pattern from the second test input node to a second test output node using a second clock signal, different from the first clock signal. A control circuit may be configured to determine whether to enable the particular lockup latch using a particular scan test signal.

    POWER DROOP MEASUREMENTS USING ANALOG-TO-DIGITAL CONVERTER DURING TESTING
    13.
    发明申请
    POWER DROOP MEASUREMENTS USING ANALOG-TO-DIGITAL CONVERTER DURING TESTING 审中-公开

    公开(公告)号：US20200319248A1

    公开(公告)日：2020-10-08

    申请号：US16375344

    申请日：2019-04-04

    Applicant: Apple Inc.

    Inventor： Bibo Li ,  Bo Yang ,  Vijay M. Bettada ,  Matthias Knoth ,  Toshinari Takayanagi

    IPC: G01R31/317 ,  G01R19/00 ,  G01R31/3177 ,  H03M1/12

    Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

    Compressed scan testing techniques
    15.
    发明授权
    Compressed scan testing techniques 有权
    压缩扫描测试技术

    公开(公告)号：US09519026B2

    公开(公告)日：2016-12-13

    申请号：US14502284

    申请日：2014-09-30

    Applicant: Apple Inc.

    Inventor： Bibo Li ,  Andrew J. Copperhall ,  Bo Yang

    IPC: G01R31/28 ,  G01R31/3185

    CPC classification number: G01R31/318566 ,  G01R31/318544

    Abstract: Techniques are disclosed relating to test equipment. In one embodiment, a method includes receiving failure information from a first test of a device under test (DUT). In this embodiment, the DUT includes a plurality of scan chains that each include a plurality of scan cells. In this embodiment, the first test is based on a first compressed test pattern. In this embodiment, the failure information does not permit a definitive determination as to which scan cell is a failing scan cell. In this embodiment, the method includes generating a plurality of compressed test patterns based on the first compressed test pattern. In this embodiment, the plurality of compressed test patterns specify one-to-one-modes. In this embodiment, the method includes performing one or more second tests of the DUT using the plurality of compressed test patterns to definitively determine one or more failing scan cells.

    Abstract translation: 公开了与测试设备有关的技术。 在一个实施例中，一种方法包括从被测设备（DUT）的第一测试接收故障信息。 在该实施例中，DUT包括多个扫描链，每条扫描链包括多个扫描单元。 在该实施例中，第一测试基于第一压缩测试图案。 在本实施例中，故障信息不能确定哪个扫描单元是故障扫描单元。 在该实施例中，该方法包括基于第一压缩测试图案生成多个压缩测试图案。 在该实施例中，多个压缩测试模式指定一对一模式。 在该实施例中，该方法包括使用多个压缩测试模式来执行DUT的一个或多个第二测试，以确定确定一个或多个故障扫描单元。

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