公开(公告)号：US20220301254A1

公开(公告)日：2022-09-22

申请号：US17205680

申请日：2021-03-18

Applicant: Apple Inc.

Inventor： Christopher A. Burns ,  Ali Rabbani Rankouhi ,  Justin A. Hensley ,  Richard W. Schreyer

IPC: G06T15/06 ,  G06T15/00 ,  G06F16/901

Abstract: Techniques are disclosed relating to ray intersection in the context of motion blur. In some embodiments, a graphics processor includes time-oblivious ray intersect circuitry configured to receive coordinates for a ray and traverse a bounding volume hierarchy (BVH) data structure based on the coordinates to determine whether the ray intersects with one or more bounding regions of a graphics space. In some embodiments, in response to reaching a temporal branch element of the BVH data structure, the ray intersect circuitry initiates a shader program that determines a sub-tree of the BVH data structure for further traversal by the ray intersection circuitry, where the sub-tree corresponds to a portion of a motion-blur interval in which the ray falls. This may provide accurate ray tracing for motion blur while reducing area and power consumption of intersect circuitry, relative to time-aware implementations.

公开(公告)号：US20220036637A1

公开(公告)日：2022-02-03

申请号：US17103317

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

IPC: G06T15/06 ,  G06T15/00 ,  G06T1/20 ,  G06F9/50 ,  G06F9/48

Abstract: Disclosed techniques relate to grouping rays during traversal of a spatially-organized acceleration data structure (e.g., a bounding volume hierarchy) for ray intersection processing. The grouping may provide temporal locality for accesses to bounding region data. In some embodiments, ray intersect circuitry is configured to group rays based on the node of the data structure that they target next. The ray intersect circuitry may select one or more groups of rays for issuance each clock cycle, e.g., to bounding region test circuitry.

公开(公告)号：US11727619B2

公开(公告)日：2023-08-15

申请号：US17352080

申请日：2021-06-18

Applicant: Apple Inc.

Inventor： Arthur Y Zhang ,  Ray L. Chang ,  Timothy R. Oriol ,  Ling Su ,  Gurjeet S. Saund ,  Guy Cote ,  Jim C. Chou ,  Hao Pan ,  Tobias Eble ,  Avi Bar-Zeev ,  Sheng Zhang ,  Justin A. Hensley ,  Geoffrey Stahl

IPC: G06T15/00 ,  H04W76/10 ,  G06F3/01 ,  G06T3/00 ,  G06T9/00 ,  H04W88/08

CPC classification number: G06T15/005 ,  G06F3/012 ,  G06T3/0093 ,  G06T9/00 ,  H04W76/10 ,  H04W88/08

Abstract: A mixed reality system that includes a device and a base station that communicate via a wireless connection The device may include sensors that collect information about the user's environment and about the user. The information collected by the sensors may be transmitted to the base station via the wireless connection. The base station renders frames or slices based at least in part on the sensor information received from the device, encodes the frames or slices, and transmits the compressed frames or slices to the device for decoding and display. The base station may provide more computing power than conventional stand-alone systems, and the wireless connection does not tether the device to the base station as in conventional tethered systems. The system may implement methods and apparatus to maintain a target frame rate through the wireless link and to minimize latency in frame rendering, transmittal, and display.

公开(公告)号：US20220375155A1

公开(公告)日：2022-11-24

申请号：US17817742

申请日：2022-08-05

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

IPC: G06T15/06 ,  G06T17/00

Abstract: Disclosed techniques relate to acceleration data structure for ray intersection testing. In some embodiments, storage circuitry stores node data for a spatially organized acceleration data structure, including to store the following node information for a given node: origin coordinates for the node and, for a given child node of multiple child nodes, child information that includes: quantized bounding region information for a bounding region corresponding to the child node, where the quantized bounding region information encodes bounding region coordinates as offsets relative to the origin coordinates. Traversal circuitry may traverse multiple nodes of the data structure and determine whether a ray intersects a bounding region indicated by given a node of the data structure based on the node information. Disclosed techniques may provide substantial improvements to performance, data size, and power consumption.

公开(公告)号：US11335061B2

公开(公告)日：2022-05-17

申请号：US17103352

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley

IPC: G06T17/10 ,  G06T15/06 ,  G06T1/20 ,  G06T15/00 ,  G06F9/50

Abstract: Disclosed techniques relate to an acceleration data structure for ray intersection with a many-to-many mapping between bounding regions and primitives. In some embodiments, one or more graphics processors access data for multiple graphics primitives in a graphics scene and generate a spatially organized data structure. Some nodes of the data structure indicate graphics primitives and some nodes indicate coordinates of bounding regions in the graphics scene. In some embodiments, the spatially organized data structure includes a node with a bounding region for which multiple primitives are indicated as children and also includes a primitive for which multiple bounding regions are indicated as parents. Disclosed techniques may generate bounding regions that closely fit primitives, which may reduce primitive testing for ray tracing. This in turn may increase performance or reduce power consumption relative to traditional techniques.

公开(公告)号：US20220036630A1

公开(公告)日：2022-02-03

申请号：US17103382

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Jonathan M. Redshaw

IPC: G06T15/00 ,  G06F16/22 ,  G06F30/31 ,  G06T15/06

Abstract: Disclosed techniques relate to forming single-instruction multiple-data (SIMD) groups during ray intersection traversal. In particular, ray intersection circuitry may include dedicated circuitry configured to traverse an acceleration data structure, but may dynamically form a SIMD group to transform ray coordinates when traversing from one level of the data structure to another. This may allow shader processors to execute the SIMD group to perform the transformation. Disclosed techniques may facilitate instancing of graphics models within the acceleration data structure.

公开(公告)号：US10755383B2

公开(公告)日：2020-08-25

申请号：US16130265

申请日：2018-09-13

Applicant: Apple Inc.

Inventor： Justin A. Hensley ,  Karl D. Mann ,  Ralph C. Taylor ,  Randall R. Rauwendaal ,  Jonathan M. Redshaw

IPC: G06T3/40 ,  G06T15/40 ,  G06F30/30 ,  G06F3/01 ,  G06T15/00 ,  G06T15/60 ,  G06F119/18

Abstract: Techniques are disclosed relating to rendering graphics objects. In some embodiments, a graphics unit is configured to transform graphics objects from a virtual space into a second space according to different transformation parameters for different portions of the second space. This may result in sampling different portions of the virtual space at different sample rates, which may reduce the number of samples required in various stages of the rendering process. In the disclosed techniques, transformation may occur prior to rasterization and shading, which may further reduce computation and power consumption in a graphics unit, improve image quality as displayed to a user, and/or reduce bandwidth usage or latency of video content on a network. In some embodiments, a transformed image may be viewed through a distortion-compensating lens or resampled prior to display.

公开(公告)号：US20180137670A1

公开(公告)日：2018-05-17

申请号：US15870081

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Christopher A. Burns ,  Justin A. Hensley

IPC: G06T15/04 ,  G06T15/06 ,  G06T15/00

CPC classification number: G06T15/04 ,  G06T15/005 ,  G06T15/06 ,  G06T2210/36

Abstract: Techniques are disclosed relating to texture sampling operations. In some embodiments, multi-fetch sampling instructions specify a region of a texture in which multiple samples are to be performed and texture processing circuitry is configured to sample the texture multiple times within the region. In some embodiments, the locations of the samples are determined according to a formula, which may be pseudo-random. In some embodiments, the locations of the samples are jittered to produce stochastic results. In some embodiments, the locations of the samples are determined based on one or more stored sets of samples that have particular properties (e.g., blue noise, in some embodiments). In various embodiments, disclosed techniques may facilitate Monte Carlo sampling.

公开(公告)号：US20170228919A1

公开(公告)日：2017-08-10

申请号：US15018252

申请日：2016-02-08

Applicant: Apple Inc.

Inventor： Christopher A. Burns ,  Justin A. Hensley

IPC: G06T15/04 ,  G06T15/06 ,  G06T15/00

CPC classification number: G06T15/04 ,  G06T15/005 ,  G06T15/06 ,  G06T2210/36

Abstract: Techniques are disclosed relating to texture sampling operations. In some embodiments, multi-fetch sampling instructions specify a region of a texture in which multiple samples are to be performed and texture processing circuitry is configured to sample the texture multiple times within the region. In some embodiments, the locations of the samples are determined according to a formula, which may be pseudo-random. In some embodiments, the locations of the samples are jittered to produce stochastic results. In some embodiments, the locations of the samples are determined based on one or more stored sets of samples that have particular properties (e.g., blue noise, in some embodiments). In various embodiments, disclosed techniques may facilitate Monte Carlo sampling.

公开(公告)号：US12265474B2

公开(公告)日：2025-04-01

申请号：US18490588

申请日：2023-10-19

Applicant: Apple Inc.

Inventor： Justin A. Hensley ,  Karl D. Mann ,  Yoong Chert Foo ,  Terence M. Potter ,  Frank W. Liljeros ,  Ralph C. Taylor

IPC: G06F12/084 ,  G06F12/1018 ,  G06F12/1036 ,  G06F30/392

Abstract: Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.