公开(公告)号：US09413354B2

公开(公告)日：2016-08-09

申请号：US14705479

申请日：2015-05-06

Applicant: Apple Inc.

Inventor： Gary L. Stirk ,  Karthik Kadirvel

IPC: H03K5/08 ,  H03K19/0175

CPC classification number: H03K19/017509 ,  G01R31/3655 ,  G01R31/3675 ,  G06F13/4256 ,  H02J7/0021 ,  H02J7/0026 ,  H02J7/0052 ,  H02J7/0068 ,  H02J7/007 ,  H02J2007/0059 ,  H03L7/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system may include a plurality of units, wherein each unit has a respective common mode voltage terminal, communication up terminal, and communication down terminal. A first unit of the plurality of units may be configured to generate a first plurality of currents on its communication up terminal, wherein the first plurality of currents corresponds to a first plurality of bits. A second unit of the plurality of units may be configured to receive the first plurality of currents on its respective communication down terminal, and maintain a voltage level at its respective communication down terminal during reception of the first plurality of currents. The voltage level may be equal to a common mode voltage of the respective common mode voltage terminal of the second unit.

Abstract translation: 系统可以包括多个单元，其中每个单元具有相应的共模电压端子，通信上行端子和通信下降端子。 多个单元中的第一单元可以被配置为在其通信上行终端上产生第一多个电流，其中第一多个电流对应于第一多个位。 多个单元中的第二单元可以被配置为在其各自的通信下行终端接收第一多个电流，并且在接收第一多个电流期间在其各自的通信下行端子处保持电压电平。 电压电平可以等于第二单元的各个共模电压端子的共模电压。

公开(公告)号：US20160178705A1

公开(公告)日：2016-06-23

申请号：US14705600

申请日：2015-05-06

Applicant: Apple Inc.

Inventor： Gary L. Stirk ,  Karthik Kadirvel

IPC: G01R31/36 ,  H02J7/00

CPC classification number: H03K19/017509 ,  G01R31/3655 ,  G01R31/3675 ,  G06F13/4256 ,  H02J7/0021 ,  H02J7/0026 ,  H02J7/0052 ,  H02J7/0068 ,  H02J7/007 ,  H02J2007/0059 ,  H03L7/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus may include one or more registers configured to store a plurality of values, and an analog-to-digital converter (ADC). Each value of the plurality of values may correspond to a characteristic of a transistor at a respective temperature value. The ADC may be configured to generate a digital value corresponding to a difference in voltage levels between a first terminal and a second terminal of the transistor. The apparatus may further include a sensor configured to measure a temperature, and control logic configured to generate a first voltage level at a control terminal of the transistor and receive the digital value from the ADC. The control logic may be further configured to determine, during a first operational mode, a current passing through the transistor dependent upon the digital value, at least one value of the plurality of values, and the temperature.

Abstract translation: 装置可以包括被配置为存储多个值的一个或多个寄存器和模数转换器（ADC）。 多个值的每个值可以对应于在相应温度值下的晶体管的特性。 ADC可以被配置为产生对应于晶体管的第一端子和第二端子之间的电压电平差的数字值。 该装置还可以包括被配置为测量温度的传感器和被配置为在晶体管的控制端产生第一电压电平并且从ADC接收数字值的控制逻辑。 控制逻辑可以进一步配置为在第一操作模式期间确定依赖于数字值，多个值中的至少一个值和温度的通过晶体管的电流。

公开(公告)号：US20180337537A1

公开(公告)日：2018-11-22

申请号：US16050325

申请日：2018-07-31

Applicant: Apple Inc.

Inventor： Karthik Kadirvel ,  Soundararajan Manthiri

IPC: H02J7/00 ,  H01M10/48 ,  H01M10/42 ,  H01M2/34 ,  H01M10/44

CPC classification number: H02J7/0026 ,  H01M2/34 ,  H01M10/425 ,  H01M10/441 ,  H01M10/482 ,  H01M2010/4271 ,  H01M2200/00 ,  H02J7/0031 ,  H02J7/0083 ,  H02J2007/0039

Abstract: This disclosure relates generally to the field of providing highly accurate over current fault protection in charging systems and, more particularly, to systems in which the charge over current protection (COCP) and discharge over current protection (DOCP) circuitry in electronic devices are particularly resilient to variations in field-effect transistor (FET) resistance with temperature, gate drive, and/or process shift; variations in printed circuit board (PCB) resistance; and variations in integrated circuit (IC) trip voltages. Through the use of novel circuit designs disclosed herein that effectively “bypass” the traditional “power FETs” that control the current flow to the battery pack(s) of the electronic device using a novel “sense FET” concept, the major sources of error in current sensing may be eliminated without compromising any safety features of the electronic device, thus allowing for more accurate over current fault protection systems for battery packs across a wide range of operating conditions and temperatures.

公开(公告)号：US09813063B2

公开(公告)日：2017-11-07

申请号：US14705600

申请日：2015-05-06

Applicant: Apple Inc.

Inventor： Gary L. Stirk ,  Karthik Kadirvel

IPC: H03K19/0175 ,  G01R31/36 ,  H02J7/00 ,  H03L7/00 ,  G06F13/42

CPC classification number: H03K19/017509 ,  G01R31/3655 ,  G01R31/3675 ,  G06F13/4256 ,  H02J7/0021 ,  H02J7/0026 ,  H02J7/0052 ,  H02J7/0068 ,  H02J7/007 ,  H02J2007/0059 ,  H03L7/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus may include one or more registers configured to store a plurality of values, and an analog-to-digital converter (ADC). Each value of the plurality of values may correspond to a characteristic of a transistor at a respective temperature value. The ADC may be configured to generate a digital value corresponding to a difference in voltage levels between a first terminal and a second terminal of the transistor. The apparatus may further include a sensor configured to measure a temperature, and control logic configured to generate a first voltage level at a control terminal of the transistor and receive the digital value from the ADC. The control logic may be further configured to determine, during a first operational mode, a current passing through the transistor dependent upon the digital value, at least one value of the plurality of values, and the temperature.

公开(公告)号：US20160093921A1

公开(公告)日：2016-03-31

申请号：US14804121

申请日：2015-07-20

Applicant: Apple Inc.

Inventor： Karthik Kadirvel ,  Soundararajan Manthiri ,  Salvatore Reddiconto ,  Liquan Tan

IPC: H01M10/42 ,  H01M2/34 ,  H01M10/48 ,  H01M2/30 ,  H02J7/00 ,  G01R31/36

CPC classification number: H01M10/425 ,  G01R31/3835 ,  G01R31/396 ,  H01M2/30 ,  H01M2/34 ,  H01M10/48 ,  H01M2010/4271 ,  H01M2200/00 ,  H02J7/0021 ,  H02J7/0026 ,  H02J7/0031 ,  H02J7/0052 ,  H02J2007/0059

Abstract: A battery system has positive and negative pack terminals, and positive and negative sense terminals. An electrochemical cell assembly has positive and negative cell terminals. An electrically conductive power path has a positive leg that connects the positive cell terminal to the positive pack terminal, and a negative leg that connects the negative cell terminal to the negative pack terminal. A power switch circuit is connected in the power path. An electrically conductive sense path separate from the power path has a positive leg that connects the positive cell terminal to the positive sense terminal, and a negative leg that connects to the negative sense terminal. A sense switch circuit is connected in the sense path. Other embodiments are also described and claimed.

Abstract translation: 电池系统具有正负极端子，正极和负极端子。 电化学电池组件具有正和负电池端子。 导电功率路径具有将正极端子连接到正极端子的正极腿和将负极端子连接到负极端子的负极腿。 电源开关电路连接在电源通路中。 与功率路径分离的导电感测通路具有将正极端子连接到正极端子的正极腿和连接到负极端子的负极腿。 感测开关电路连接在感测路径中。 还描述和要求保护其他实施例。