公开(公告)号：US10978136B2

公开(公告)日：2021-04-13

申请号：US16515351

申请日：2019-07-18

Applicant: Apple Inc.

Inventor： Liang Deng ,  Norman J. Rohrer ,  Yizhang Yang ,  Arpit Mittal

IPC: G11C7/04 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4074

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

公开(公告)号：US10483974B2

公开(公告)日：2019-11-19

申请号：US16140488

申请日：2018-09-24

Applicant: Apple Inc.

Inventor： Keith Cox ,  Victor Zyuban ,  Norman J. Rohrer

IPC: G11C5/04 ,  H03K5/01 ,  H03K19/0175 ,  G11C5/14 ,  H03K5/00 ,  H02J1/00

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

公开(公告)号：US20190052271A1

公开(公告)日：2019-02-14

申请号：US16140488

申请日：2018-09-24

Applicant: Apple Inc.

Inventor： Keith Cox ,  Victor Zyuban ,  Norman J. Rohrer

IPC: H03K19/0175 ,  H03K5/01 ,  G11C5/14 ,  H02J1/00 ,  H03K5/00

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

公开(公告)号：US20170357302A1

公开(公告)日：2017-12-14

申请号：US15275213

申请日：2016-09-23

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  Christopher W. Chaney ,  Norman J. Rohrer ,  Cyril De La Cropte De Chanterac

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/171

Abstract: Embodiments provide for a computer implemented method comprising sampling one or more power and performance metrics of a processor; determining an energy cost per instruction based on the one or more power and performance metrics; determining an efficiency metric based on the energy cost per instruction; computing an efficiency control error based on a difference between a current efficiency metric and a target efficiency metric; setting an efficiency control effort based on the efficiency control error; determining a performance control effort, the performance control effort determined by a performance controller for the processor; and adjusting the performance control effort based on the efficiency control effort, wherein adjusting the performance control effort reduces power consumption of the processor.

公开(公告)号：US09712141B2

公开(公告)日：2017-07-18

申请号：US14958783

申请日：2015-12-03

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Norman J. Rohrer

IPC: H03H11/26 ,  H03K5/04 ,  H03K17/693 ,  G05F1/46

CPC classification number: H03K5/04 ,  G05F1/46 ,  H03K17/693

Abstract: Embodiments relate to modulating a power supply voltage for varying a propagation delay of data paths within an integrated circuit. The power supply voltage is modulated to increase the delay of shorter data paths for reducing an incidence of hold time violations without substantially affecting the delay of longer data paths. For example, the power supply voltage is reduced from a nominal value in the first half clock cycle to increase delay of both the shorter data paths and the longer data paths. The power supply voltage is increased from the nominal value in the second half clock cycle to decrease delay of the longer data paths within the second half clock cycle such that the overall delay of the longer data paths is virtually same as when the power supply voltage is fixed at the nominal value for the entire clock cycle.

公开(公告)号：US20170163248A1

公开(公告)日：2017-06-08

申请号：US14958783

申请日：2015-12-03

Applicant: Apple Inc.

Inventor： Victor Zyuban ,  Norman J. Rohrer

IPC: H03K5/04 ,  G05F1/46 ,  H03K17/693

CPC classification number: H03K5/04 ,  G05F1/46 ,  H03K17/693

Abstract: Embodiments relate to modulating a power supply voltage for varying a propagation delay of data paths within an integrated circuit. The power supply voltage is modulated to increase the delay of shorter data paths for reducing an incidence of hold time violations without substantially affecting the delay of longer data paths. For example, the power supply voltage is reduced from a nominal value in the first half clock cycle to increase delay of both the shorter data paths and the longer data paths. The power supply voltage is increased from the nominal value in the second half clock cycle to decrease delay of the longer data paths within the second half clock cycle such that the overall delay of the longer data paths is virtually same as when the power supply voltage is fixed at the nominal value for the entire clock cycle.

公开(公告)号：US11823728B2

公开(公告)日：2023-11-21

申请号：US17687107

申请日：2022-03-04

Applicant: Apple Inc.

Inventor： Liang Deng ,  Norman J. Rohrer ,  Yizhang Yang ,  Arpit Mittal

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091

CPC classification number: G11C11/40626 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2211/4061

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

公开(公告)号：US11418194B2

公开(公告)日：2022-08-16

申请号：US17399933

申请日：2021-08-11

Applicant: Apple Inc.

Inventor： Keith Cox ,  Victor Zyuban ,  Norman J. Rohrer

IPC: H02J1/00 ,  H03K19/0175 ,  H03K5/01 ,  G11C5/14 ,  H03K5/00 ,  H02J1/08

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

公开(公告)号：US11270753B2

公开(公告)日：2022-03-08

申请号：US17182341

申请日：2021-02-23

Applicant: Apple Inc.

Inventor： Liang Deng ,  Norman J. Rohrer ,  Yizhang Yang ,  Arpit Mittal

IPC: G11C7/04 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

公开(公告)号：US20210376831A1

公开(公告)日：2021-12-02

申请号：US17399933

申请日：2021-08-11

Applicant: Apple Inc.

Inventor： Keith Cox ,  Victor Zyuban ,  Norman J. Rohrer

IPC: H03K19/0175 ,  H03K5/01 ,  G11C5/14

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.