公开(公告)号：US20160241240A1

公开(公告)日：2016-08-18

申请号：US14622111

申请日：2015-02-13

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Harsha Krishnamurthy ,  Edvin Catovic ,  Rajat Goel ,  Manoj Gopalan

IPC: H03K19/003 ,  H03K19/00

CPC classification number: H03K19/00361 ,  H03K19/0013 ,  H03K19/0016

Abstract: In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个电源门控块和功率管理器电路。 功率管理器电路可以被配置为为每个电源门控块和块使能时钟生成块使能。 电源门控块可以在电源门控块中产生各种电源开关段的本地块使能。 特别地，电源门控块可以包括从电源管理器电路接收块使能的一组串联的触发器。 功率门控块可以包括为每个功率开关段提供本地块使能的一组多路复用器（多路复用器）。 多路复用器的一个输入耦合到块使能，另一个输入耦合到通过其它功率开关段之一传播的另一个功能。 因此，可以控制多路复用器来选择传播的使能或输入块使能。

公开(公告)号：US20140215191A1

公开(公告)日：2014-07-31

申请号：US13750972

申请日：2013-01-25

Applicant: APPLE INC.

Inventor： Pradeep Kanapathipillai ,  Hari Kannan ,  Po-Yung Chang ,  Ming-Ta Hsu ,  Rajat Goel

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3834

Abstract: Techniques are disclosed relating to ordering of load instructions in a weakly-ordered memory model. In one embodiment, a processor includes a cache with multiple cache lines and a store queue configured to maintain status information associated with a store instruction that targets a location in one of the cache lines. In this embodiment, the processor is configured to set an indicator in the status information in response to migration of the targeted cache line. The indicator may be usable to sequence performance of load instructions that are younger than the store instruction. For example, the processor may be configured to wait, based on the indicator, to perform a younger load instruction that targets the same location as the store instruction until the store instruction is removed from the store queue. This may prevent forwarding of the value of the store instruction to the younger load and preserve load-load ordering.

Abstract translation: 公开了关于弱有序存储器模型中的加载指令的排序的技术。 在一个实施例中，处理器包括具有多个高速缓存行的高速缓存和存储队列，该存储队列被配置为维护与存储指令相关联的状态信息，所述存储指令针对高速缓存行之一中的位置 在该实施例中，处理器被配置为响应于目标高速缓存线的迁移而将状态信息中的指示符设置成。 该指示符可用于对比小于存储指令的加载指令的性能进行排序。 例如，处理器可以被配置为基于指示符等待执行与存储指令相同的位置的较年轻的加载指令，直到存储指令从存储队列中移除。 这可能会阻止将存储指令的值转发到较小的负载并保持负载负载顺序。

公开(公告)号：US20140215190A1

公开(公告)日：2014-07-31

申请号：US13750942

申请日：2013-01-25

Applicant: APPLE INC.

Inventor： John H. Mylius ,  Rajat Goel ,  Pradeep Kanapathipillai ,  Hari S. Kannan

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855

Abstract: Techniques are disclosed relating to completion of load and store instructions in a weakly-ordered memory model. In one embodiment, a processor includes a load queue and a store queue and is configured to associate queue information with a load instruction in an instruction stream. In this embodiment, the queue information indicates a location of the load instruction in the load queue and one or more locations in the store queue that are associated with one or more store instructions that are older than the load instruction. The processor may determine, using the queue information, that the load instruction does not conflict with a store instruction in the store queue that is older than the load instruction. The processor may remove the load instruction from the load queue while the store instruction remains in the store queue. The queue information may include a wrap value for the load queue.

Abstract translation: 公开了在弱有序存储器模型中完成负载和存储指令的技术。 在一个实施例中，处理器包括加载队列和存储队列，并且被配置为将队列信息与指令流中的加载指令相关联。 在该实施例中，队列信息指示加载队列中的加载指令的位置和存储队列中与一个或多个比加载指令更早的存储指令相关联的一个或多个位置。 处理器可以使用队列信息来确定加载指令不与存储队列中比加载指令更早的存储指令冲突。 当存储指令保留在存储队列中时，处理器可以从加载队列中移除加载指令。 队列信息可以包括加载队列的换行值。