公开(公告)号：US20170075760A1

公开(公告)日：2017-03-16

申请号：US14850992

申请日：2015-09-11

Applicant: ARM LIMITED

Inventor： Emre ÖZER ,  Balaji VENU

IPC: G06F11/10

CPC classification number: G06F11/1012 ,  G06F11/10 ,  G06F11/1076

Abstract: A state indicating value is encoded with a one-hot or one-cold encoding and each bit of the state indicating value is stored in a different portion of a storage element. Parity values are determined for each portion of the storage element and stored to a parity storage element. This allows errors caused by single event upsets or multi-bit upsets to be detected and corrected, with lower hardware cost compared to alternative approaches.

Abstract translation: 状态指示值用单热或单冷编码编码，状态指示值的每一位都存储在存储元件的不同部分。 为存储元件的每个部分确定奇偶校验值，并存储到奇偶校验存储元件。 这允许检测和纠正由单个事件发生或多个位发生故障引起的错误，与替代方法相比，具有较低的硬件成本。

公开(公告)号：US20250036632A1

公开(公告)日：2025-01-30

申请号：US18226334

申请日：2023-07-26

Applicant: Arm Limited

Inventor： Damian Piotr MODRZYK ,  Metin Gokhan ÜNAL ,  Giacomo GABRIELLI ,  Balaji VENU

IPC: G06F16/2455 ,  G06F16/2453

Abstract: Provided is a data stream processor comprising a streamed data transceiver interface, a structure of processing units configurable to transform data received from a data source over the streamed data transceiver interface according to a specified output requirement, and a configuration unit operable in electronic communication with a data consumer to receive an output requirement and to configure the operation and linkage of a processing unit in the structure of processing units to transform input data to output data according to the specified output requirement; wherein the structure of processing units is further operable to provide the output data for output over the streamed data transceiver interface.

公开(公告)号：US20240086202A1

公开(公告)日：2024-03-14

申请号：US17942554

申请日：2022-09-12

Applicant: Arm Limited

Inventor： Matthew James WALKER ,  Mbou EYOLE ,  Giacomo GABRIELLI ,  Balaji VENU ,  Wei WANG

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/3855 ,  G06F9/30145 ,  G06F9/32

Abstract: An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.

公开(公告)号：US20210279124A1

公开(公告)日：2021-09-09

申请号：US17261217

申请日：2019-06-06

Applicant: Arm Limited

Inventor： Milosch MERIAC ,  Emre ÖZER ,  Xabier ITURBE ,  Balaji VENU ,  Shidhartha DAS

IPC: G06F11/07 ,  G06F11/16 ,  G06F11/20 ,  G06F11/30

Abstract: An apparatus comprises a plurality of redundant processing units (4) to perform data processing redundantly in lockstep; common mode fault detection circuitry *6, 22) to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory (10) shared between the plurality of redundant processing units; and memory checking circuitry (30) to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry (30) performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry (6, 22) indicating that the event indicative of a potential common mode fault has been detected.

公开(公告)号：US20200174863A1

公开(公告)日：2020-06-04

申请号：US16206189

申请日：2018-11-30

Applicant: Arm Limited

Inventor： Reiley JEYAPAUL ,  Balaji VENU

IPC: G06F11/00 ,  G06F17/50

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

公开(公告)号：US20190391888A1

公开(公告)日：2019-12-26

申请号：US16014154

申请日：2018-06-21

Applicant: Arm Limited

Inventor： Milosch MERIAC ,  Xabier ITURBE ,  Emre OZER ,  Balaji VENU ,  Shidhartha DAS

IPC: G06F11/20 ,  G06F11/14 ,  G06F11/16

Abstract: Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.