公开(公告)号：US20240248755A1

公开(公告)日：2024-07-25

申请号：US18099595

申请日：2023-01-20

Applicant: Arm Limited

Inventor： Rune HOLM ,  Jens OLSON ,  Jared Corey SMOLENS ,  Dominic Hugo SYMES ,  Elliot Maurice Simon ROSEMARINE

IPC: G06F9/48 ,  G06F9/355

CPC classification number: G06F9/4881 ,  G06F9/3555

Abstract: A processor comprising: a handling unit; a plurality of components each configured to execute a function. The handling unit can receive a task comprising operations on data in a coordinate space having N dimensions, receive a data structure describing execution of the task and comprising a partially ordered set of data items each associated with instructions usable by the plurality of components when executing the task, each data item is associated with a component among the plurality of components, each data item indicates dimensions of the coordinates space for which changes of coordinate causes the function of the associated component to execute, and dimensions of the coordinate space for which changes of coordinate causes the function of the associated component to store data ready to be used by another component. The handling unit iterates over the coordinate space and executes the task using the partially ordered set of data items.

公开(公告)号：US20210374422A1

公开(公告)日：2021-12-02

申请号：US16888068

申请日：2020-05-29

Applicant: Arm Limited

Inventor： Jayavarapu Srinivasa RAO ,  Daren CROXFORD ,  Dominic Hugo SYMES

IPC: G06K9/00 ,  G06K9/62 ,  G06N3/04 ,  G06N3/08

Abstract: A method is described for operating on a frame of a video to generate a feature map of a neural network. The method determines if a block of the frame is an inter block or an intra block, and performs an inter block process in the event that the block is an inter block and/or an intra block process in the event that the block is an intra block. The inter block process determines a measure of differences between the block of the frame and a reference block of a reference frame of the video, and performs either a first process or a second process based on the measure to generate a segment of the feature map. The intra block process determines a measure of flatness of the block of the frame, and performs either a third process or a fourth process based on the measure to generate a segment of the feature map.

公开(公告)号：US20130322550A1

公开(公告)日：2013-12-05

申请号：US13863607

申请日：2013-04-16

Applicant: ARM Limited

Inventor： Dominic Hugo SYMES

IPC: H04N7/26

CPC classification number: H04N19/43 ,  H04N19/436 ,  H04N19/44

Abstract: A video decoding apparatus for decoding an encoded video bitstream having a sequence of video pictures, wherein at least one video picture is encoded in a plurality of slices, wherein each slice comprises a sequence of raster scan order blocks which can be decoded independently of another slice. The video decoding apparatus comprises: an array store configured to store an array of values, with an array entry corresponding to each block position in the video picture, such that each block position has its own corresponding array entry; a plurality of parsing units each configured to perform a parsing operation on a selected sequence of raster scan order blocks in a selected slice and to write a value to a selected array entry corresponding to a first block in the selected sequence, the value indicating a location of parsed data generated by the parsing operation and required to render the selected sequence of blocks; and a rendering unit configured to render the video pictures using the parsed data with reference to the values written to the array store, wherein the plurality of parsing units are configured to perform their respective parsing operations on the plurality of slices in parallel with each other.

Abstract translation: 一种视频解码装置，用于对具有视频图像序列的编码视频比特流进行解码，其中至少一个视频图像被编码在多个切片中，其中每个切片包括一系列光栅扫描顺序块，其可以独立于另一个切片 。 视频解码装置包括：数组存储器，被配置为存储数组数组，其中阵列条目对应于视频图像中的每个块位置，使得每个块位置具有其自己的相应阵列条目; 多个解析单元，每个解析单元被配置为对所选片段中的所选择的光栅扫描顺序序列序列执行解析操作，并将值写入对应于所选序列中的第一块的所选择的阵列条目，该值指示位置 由解析操作产生的解析数据，并且需要渲染所选择的块序列; 以及渲染单元，被配置为参考写入到阵列存储器的值，使用解析的数据渲染视频图像，其中多个解析单元被配置为相互并行地对多个片段执行它们各自的解析操作。

公开(公告)号：US20220014767A1

公开(公告)日：2022-01-13

申请号：US17296432

申请日：2019-12-03

Applicant: ARM LIMITED

Inventor： Dominic Hugo SYMES ,  Sven Ola Johannes HUGOSSON

IPC: H04N19/34 ,  H04N19/176

Abstract: Disclosed herein is a method of encoding an array of data elements comprising transforming the array from the spatial to the frequency domain, representing the frequency domain coefficients as a plurality of bit plane arrays, and encoding the set of frequency domain coefficients as a data packet having a fixed size by encoding the bit plane arrays in a bit plane sequence working from the bit plane array representing the most significant bit downwards until the data packet is full. Each bit plane array is encoded by recursively subdividing the bit plane array into respective sections and subsections down to the individual coefficients and including in the data packet, so long as there is available space, data indicating the locations of any (sub)sections in that bit plane array that for the first time in the bit plane sequence contain one or more coefficient(s) having a non-zero bit value.

公开(公告)号：US20150237346A1

公开(公告)日：2015-08-20

申请号：US14596971

申请日：2015-01-14

Applicant: ARM Limited

Inventor： Dominic Hugo SYMES ,  Ola HUGOSSON ,  Erik PERSSON

IPC: H04N19/124 ,  H04N19/13 ,  H04N19/91 ,  H04N19/176

CPC classification number: H04N19/124 ,  H04N19/13 ,  H04N19/15 ,  H04N19/176 ,  H04N19/91

Abstract: A video encoder and method of video encoding are provided. At an encoding stage a selected degree of quantization is applied to the encoding of macroblocks of the input video sequence and quantized part-encoded macroblocks are generated. Quantization circuitry in the encoding stage is configured to select the selected degree of quantization for each macroblock in a current slice in dependence on a complexity estimate indicative of the expected entropy encoding complexity of a predetermined set of the quantized part-encoded macroblocks defined for that macroblock.

Abstract translation: 提供视频编码器和视频编码方法。 在编码阶段，将选择的量化量应用于输入视频序列的宏块的编码，并生成量化的部分编码的宏块。 编码级中的量化电路被配置为根据指定针对该宏块定义的量化部分编码宏块的预定熵编码复杂度的复杂度估计，在当前片中为每个宏块选择所选择的量化度 。

公开(公告)号：US20140337396A1

公开(公告)日：2014-11-13

申请号：US14225473

申请日：2014-03-26

Applicant: ARM LIMITED

Inventor： Dominic Hugo SYMES ,  Tomas EDSO

IPC: G06F17/14

CPC classification number: G06F17/147 ,  H04N19/625

Abstract: A data processing apparatus and method are provided for performing a transform between spatial and frequency domains when processing video data. The data processing apparatus comprises transform circuitry configured to receive N input values and to perform a sequence of operations to generate N output values representing the transform of the N input values between the spatial and frequency domains. In doing this, the transform circuitry employs a base circuitry that is configured to receive M internal input values generated by the transform circuitry, where M is greater than or equal to 4, and to perform a base operation equivalent to matrix multiplication of the M internal input values by a Hankel matrix, which is a square matrix with constant skew diagonals, where each element of the array identifies a coefficient, performance of the base operation generating M internal output values for returning to the transform circuitry. The transform circuitry is arranged during performance of the sequence of operations to generate from the N input values multiple sets of the M internal input values, to provide each set of M internal input values to the base circuitry in order to cause multiple sets of the M internal output values to be produced, and to derive the N output values from the multiple sets of M internal output values. It has been found that such an approach is scalable to accommodate varying sizes of N, results in a significant reduction in the number of multiplications required in order to perform the transform between the spatial and frequency domains of the N input values, and produces a bit exact result.

Abstract translation: 提供了一种数据处理装置和方法，用于在处理视频数据时执行空域与频域之间的变换。 数据处理装置包括被配置为接收N个输入值并且执行一系列操作以产生表示空间和频域之间的N个输入值的变换的N个输出值的变换电路。 在这样做时，变换电路采用基本电路，其被配置为接收由变换电路产生的M个内部输入值，其中M大于或等于4，并且执行等效于M内部的矩阵乘法的基本操作 输入值由Hankel矩阵，其是具有恒定偏斜对角线的方阵，其中阵列的每个元素识别系数，基本运算的性能产生用于返回到变换电路的M个内部输出值。 变换电路在执行操作序列期间被布置，以从N个输入值生成多组M个内部输入值，以将每组M个内部输入值提供给基本电路，以便产生多组M 要产生的内部输出值，并从多组M个内部输出值中导出N个输出值。 已经发现，这种方法是可扩展的以适应N的不同大小，导致为了执行N个输入值的空间域和频域之间的变换所需的乘法数量的显着减少，并且产生一个位 确切的结果。

公开(公告)号：US20140283117A1

公开(公告)日：2014-09-18

申请号：US14173418

申请日：2014-02-05

Applicant: ARM LIMITED

Inventor： Ola HUGOSSON ,  Erik PERSSON ,  Dominic Hugo SYMES

IPC: G06F21/62

CPC classification number: G06F21/6218 ,  G06F21/78

Abstract: A data processing apparatus is provided, comprising plural processing units configured to execute plural processes, a storage unit configured to store data required for the plural processes; and a protection unit configured to control access by the plural processes to the storage unit. The protection unit is configured to define an allocated access region of the storage unit for each process of the plural processes, wherein the protection unit is configured to deny access for each the process outside the allocated access region and wherein allocated access regions are defined to be non-overlapping. The protection unit is configured to define each allocated access region as a contiguous portion of the storage unit between a lower region limit and an upper region limit, and the protection unit is configured such that when the lower region limit is modified the lower region limit cannot be decreased and such that when the upper region limit is modified the upper region limit cannot be decreased.

Abstract translation: 提供了一种数据处理装置，包括被配置为执行多个处理的多个处理单元，被配置为存储多个处理所需的数据的存储单元; 以及保护单元，被配置为控制通过所述多个处理对所述存储单元的访问。 保护单元被配置为为多个进程的每个进程定义存储单元的分配的访问区域，其中保护单元被配置为拒绝对所分配的访问区域之外的每个进程的访问，并且其中分配的访问区域被定义为 不重叠。 保护单元被配置为将每个分配的访问区域定义为存储单元在下限区域和上区域限制之间的连续部分，并且保护单元被配置为使得当下区域限制被修改时，下区域限制不能 并且使得当上限区域被修改时，上限区域不能减小。

公开(公告)号：US20130276096A1

公开(公告)日：2013-10-17

申请号：US13777309

申请日：2013-02-26

Applicant: ARM LIMITED

Inventor： Dominic Hugo SYMES ,  Ola HUGOSSON ,  Donald FELTON ,  Erik PERSSON

IPC: G06F21/60

CPC classification number: G06F21/606 ,  G06F12/1027 ,  G06F12/1072 ,  G06F21/74 ,  G06F2212/302

Abstract: A data processing apparatus is configured to perform secure data processing operations and non-secure data processing operations, wherein the apparatus includes a master device with a secure domain and a non-secure domain. Components of the master device operate in the secure domain when performing secure data processing operations and operate in the non-secure domain when performing the non-secure data processing operations. A slave device is configured to perform a delegated data processing operation specified by the master device and a communication bus connecting the master device to the slave device. The delegated operation is initiated by an issuing component in the master device, wherein the slave device includes a security inheritance mechanism configured to cause the delegated operation to inherit a non-secure security status or a secure status depending upon whether the issuing component in the master device is operating in the non-secure domain or the secure domain.

Abstract translation: 数据处理装置被配置为执行安全数据处理操作和非安全数据处理操作，其中该装置包括具有安全域和非安全域的主设备。 当执行安全数据处理操作时，主设备的组件在安全域中操作，并且在执行非安全数据处理操作时在非安全域中操作。 从设备被配置为执行由主设备指定的委托数据处理操作和将主设备连接到从设备的通信总线。 委托操作由主设备中的发布组件启动，其中从设备包括安全继承机制，该安全继承机制被配置为使得委托操作继承非安全安全状态或安全状态，这取决于主设备中的发布组件 设备在非安全域或安全域中运行。