公开(公告)号：US20190098324A1

公开(公告)日：2019-03-28

申请号：US16199624

申请日：2018-11-26

Applicant: ARM Limited

Inventor： Ola HUGOSSON ,  Dominic Hugo SYMES

IPC: H04N19/436 ,  H04N19/44 ,  H04N19/172

Abstract: A video decoder configured to decode an encoded video bitstream comprises a first parsing unit and a second parsing unit, each configured to independently parse the encoded video bitstream to derive parsing state information therefrom on which subsequent parsing of the encoded video bitstream at least partially depends and to identify macroblock information for decoding. The encoded video bitstream comprises frame header information defining a sequence of frames and each frame is composed of macroblocks represented by macroblock information. A control unit of the video encoder allocates each frame of macroblock information to one of the two parsing units to parse. The two parsing units are both configured to parse frame header information to thereby each derive parsing state information for the encoded video bitstream, and the two parsing unit are each configured to parse macroblock information allocated to them, skipping macroblock information allocated to the other parsing unit.

公开(公告)号：US20150169452A1

公开(公告)日：2015-06-18

申请号：US14557649

申请日：2014-12-02

Applicant: ARM LIMITED

Inventor： Erik PERSSON ,  Ola HUGOSSON

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/0895

Abstract: A data processing apparatus and corresponding method of data processing are provided. The data processing apparatus comprises a temporary data store configured to store data items retrieved from a memory, wherein the temporary data store selects one of its plural data storage locations in which to store a newly retrieved data item according to a predetermined circular sequence. An index data store is configured to store index items corresponding to the data items stored in the temporary data store, wherein presence of a valid index item in the index data store is indicative of a corresponding data item in the temporary data store. Invalidation control circuitry performs a rolling invalidation process with respect to the index items stored in the index data store, comprising sequentially processing the index items stored in the index data store and selectively marking the index items as invalid according to a predetermined criterion.

Abstract translation: 提供了一种数据处理装置和相应的数据处理方法。 数据处理装置包括临时数据存储器，被配置为存储从存储器检索的数据项，其中临时数据存储器根据预定的循环序列选择其中存储新检索的数据项的多个数据存储位置中的一个。 索引数据存储器被配置为存储与存储在临时数据存储中的数据项相对应的索引项，其中，索引数据存储中的有效索引项的存在指示临时数据存储中的对应的数据项。 无效化控制电路对存储在索引数据存储器中的索引项执行滚动无效处理，包括依次处理存储在索引数据存储器中的索引项，并根据预定标准有选择地将索引项标记为无效。

公开(公告)号：US20150089148A1

公开(公告)日：2015-03-26

申请号：US14560464

申请日：2014-12-04

Applicant: ARM Limited

Inventor： Erik PERSSON ,  Ola HUGOSSON ,  Andreas BJORKLUND

IPC: G06F12/10 ,  G06F12/12

CPC classification number: G06F12/1018 ,  G06F12/1027 ,  G06F12/122

Abstract: A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided.

Abstract translation: 提供了一种数据处理装置，包括被配置为发布包括虚拟地址的存储器访问请求的多个主设备。 存储器管理单元被配置为接收存储器访问请求并将包括在存储器访问请求中的虚拟地址从请求主设备转换成指示存储器中的存储位置的物理地址。 存储器管理单元具有内部存储单元，其具有多个条目，其中存储对应的虚拟地址部分和物理地址部分的指示。 存储器管理单元被配置为根据虚拟地址和请求主设备的标识符来选择内部存储单元的条目。 因此避免了主设备在使用内部存储单元时的冲突。

公开(公告)号：US20130275701A1

公开(公告)日：2013-10-17

申请号：US13777338

申请日：2013-02-26

Applicant: ARM LIMITED

Inventor： Dominic Hugo SYMES ,  Ola HUGOSSON ,  Donald FELTON ,  Sean Tristram ELLIS

IPC: G06F12/14

CPC classification number: G06F12/145

Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of descriptors defining the translations, wherein the page table base address is defined by the primary processor and cannot be amended by the secondary processor.

Abstract translation: 数据处理装置包括主处理器，被配置为执行安全数据处理操作和非安全数据处理操作的辅助处理器，以及被配置为在执行安全数据处理操作时存储由辅助处理器使用的安全数据的存储器，并且被配置为存储 在执行非安全数据处理操作时由辅助处理器使用的非安全数据，其中所述安全数据不能被所述非安全数据处理操作访问，其中所述辅助处理器包括存储器管理单元，所述存储器管理单元被配置为管理对 来自二级处理器的存储器，所述存储器管理单元被配置为在所述辅助处理器使用的虚拟存储器地址和所述存储器使用的物理存储器地址之间执行转换，其中，所述转换根据页表基地址，所述页表基 地址识别存储位置 定义翻译的一组描述符的存储器，其中页表基地址由主处理器定义并且不能被辅助处理器修改。

公开(公告)号：US20150237346A1

公开(公告)日：2015-08-20

申请号：US14596971

申请日：2015-01-14

Applicant: ARM Limited

Inventor： Dominic Hugo SYMES ,  Ola HUGOSSON ,  Erik PERSSON

IPC: H04N19/124 ,  H04N19/13 ,  H04N19/91 ,  H04N19/176

CPC classification number: H04N19/124 ,  H04N19/13 ,  H04N19/15 ,  H04N19/176 ,  H04N19/91

Abstract: A video encoder and method of video encoding are provided. At an encoding stage a selected degree of quantization is applied to the encoding of macroblocks of the input video sequence and quantized part-encoded macroblocks are generated. Quantization circuitry in the encoding stage is configured to select the selected degree of quantization for each macroblock in a current slice in dependence on a complexity estimate indicative of the expected entropy encoding complexity of a predetermined set of the quantized part-encoded macroblocks defined for that macroblock.

Abstract translation: 提供视频编码器和视频编码方法。 在编码阶段，将选择的量化量应用于输入视频序列的宏块的编码，并生成量化的部分编码的宏块。 编码级中的量化电路被配置为根据指定针对该宏块定义的量化部分编码宏块的预定熵编码复杂度的复杂度估计，在当前片中为每个宏块选择所选择的量化度 。

公开(公告)号：US20140283117A1

公开(公告)日：2014-09-18

申请号：US14173418

申请日：2014-02-05

Applicant: ARM LIMITED

Inventor： Ola HUGOSSON ,  Erik PERSSON ,  Dominic Hugo SYMES

IPC: G06F21/62

CPC classification number: G06F21/6218 ,  G06F21/78

Abstract: A data processing apparatus is provided, comprising plural processing units configured to execute plural processes, a storage unit configured to store data required for the plural processes; and a protection unit configured to control access by the plural processes to the storage unit. The protection unit is configured to define an allocated access region of the storage unit for each process of the plural processes, wherein the protection unit is configured to deny access for each the process outside the allocated access region and wherein allocated access regions are defined to be non-overlapping. The protection unit is configured to define each allocated access region as a contiguous portion of the storage unit between a lower region limit and an upper region limit, and the protection unit is configured such that when the lower region limit is modified the lower region limit cannot be decreased and such that when the upper region limit is modified the upper region limit cannot be decreased.

Abstract translation: 提供了一种数据处理装置，包括被配置为执行多个处理的多个处理单元，被配置为存储多个处理所需的数据的存储单元; 以及保护单元，被配置为控制通过所述多个处理对所述存储单元的访问。 保护单元被配置为为多个进程的每个进程定义存储单元的分配的访问区域，其中保护单元被配置为拒绝对所分配的访问区域之外的每个进程的访问，并且其中分配的访问区域被定义为 不重叠。 保护单元被配置为将每个分配的访问区域定义为存储单元在下限区域和上区域限制之间的连续部分，并且保护单元被配置为使得当下区域限制被修改时，下区域限制不能 并且使得当上限区域被修改时，上限区域不能减小。

公开(公告)号：US20130276096A1

公开(公告)日：2013-10-17

申请号：US13777309

申请日：2013-02-26

Applicant: ARM LIMITED

Inventor： Dominic Hugo SYMES ,  Ola HUGOSSON ,  Donald FELTON ,  Erik PERSSON

IPC: G06F21/60

CPC classification number: G06F21/606 ,  G06F12/1027 ,  G06F12/1072 ,  G06F21/74 ,  G06F2212/302

Abstract: A data processing apparatus is configured to perform secure data processing operations and non-secure data processing operations, wherein the apparatus includes a master device with a secure domain and a non-secure domain. Components of the master device operate in the secure domain when performing secure data processing operations and operate in the non-secure domain when performing the non-secure data processing operations. A slave device is configured to perform a delegated data processing operation specified by the master device and a communication bus connecting the master device to the slave device. The delegated operation is initiated by an issuing component in the master device, wherein the slave device includes a security inheritance mechanism configured to cause the delegated operation to inherit a non-secure security status or a secure status depending upon whether the issuing component in the master device is operating in the non-secure domain or the secure domain.

Abstract translation: 数据处理装置被配置为执行安全数据处理操作和非安全数据处理操作，其中该装置包括具有安全域和非安全域的主设备。 当执行安全数据处理操作时，主设备的组件在安全域中操作，并且在执行非安全数据处理操作时在非安全域中操作。 从设备被配置为执行由主设备指定的委托数据处理操作和将主设备连接到从设备的通信总线。 委托操作由主设备中的发布组件启动，其中从设备包括安全继承机制，该安全继承机制被配置为使得委托操作继承非安全安全状态或安全状态，这取决于主设备中的发布组件 设备在非安全域或安全域中运行。