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公开(公告)号：US20230080578A1
公开(公告)日：2023-03-16
申请号：US17474619
申请日：2021-09-14
Applicant: Arm Limited
Inventor： Dominic Hugo SYMES , Fredrik Peter STOLT
Abstract: A dot product array comprises dot product circuits each to process a respective pair of first and second input vectors to generate a respective dot product result. In a real number mode, each dot product result and vector element represents a respective real number. In a hypercomplex number mode, an input vector manipulation is applied to at least one of the first/second input vectors to be supplied to each dot product circuit, to cause the dot product array to generate hypercomplex dot product results each indicating a sum of hypercomplex products of corresponding pairs of hypercomplex numbers. In the hypercomplex number mode, respective subsets of elements of the first/second input vectors represent respective hypercomplex numbers, for which respective components are represented by different elements of the subset, and each hypercomplex dot product result comprises components represented by the dot product results generated by a corresponding group of at least two dot product circuits.
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公开(公告)号：US20190098324A1
公开(公告)日：2019-03-28
申请号：US16199624
申请日：2018-11-26
Applicant: ARM Limited
Inventor： Ola HUGOSSON , Dominic Hugo SYMES
IPC: H04N19/436 , H04N19/44 , H04N19/172
Abstract: A video decoder configured to decode an encoded video bitstream comprises a first parsing unit and a second parsing unit, each configured to independently parse the encoded video bitstream to derive parsing state information therefrom on which subsequent parsing of the encoded video bitstream at least partially depends and to identify macroblock information for decoding. The encoded video bitstream comprises frame header information defining a sequence of frames and each frame is composed of macroblocks represented by macroblock information. A control unit of the video encoder allocates each frame of macroblock information to one of the two parsing units to parse. The two parsing units are both configured to parse frame header information to thereby each derive parsing state information for the encoded video bitstream, and the two parsing unit are each configured to parse macroblock information allocated to them, skipping macroblock information allocated to the other parsing unit.
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公开(公告)号：US20230186045A1
公开(公告)日：2023-06-15
申请号：US17938217
申请日：2022-10-05
Applicant: Arm Limited
Inventor： Dominic Hugo SYMES , Robert NORBERG , Tomas Fredrik EDSÖ , Rajanarayana Priyanka MARIGI , Douglas William TROHA
IPC: G06N3/02
CPC classification number: G06N3/02
Abstract: A sequence of operations to process an initial input data array for the sequence of operations to generate a final output data array of the sequence of operations on a processor operable to execute neural network processing, the sequence are performed for respective blocks of the initial input data array on a block-by-block basis, and when performing an operation in the sequence whose output data is input data for another operation in the sequence, the output data is used as input data for another operation of the sequence is stored in local storage of the processor that is performing the neural network processing, and provided as input data for the another operation in the sequence from the local storage, but for the final operation in the sequence, the final output data array is stored in a main memory of the data processing system.
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公开(公告)号：US20220038270A1
公开(公告)日：2022-02-03
申请号：US16940770
申请日：2020-07-28
Applicant: Arm Limited
Inventor： Sharjeel SAEED , Daren CROXFORD , Dominic Hugo SYMES
Abstract: A data processing system including storage. The data processing system also includes at least one processor to generate output data using at least a portion of a first neural network layer and generate a key associated with at least the portion of the first neural network layer. The at least one processor is further operable to obtain the key from the storage and obtain a version of the output data for input into a second neural network layer. Using the key, the at least one processor is further operable to determine whether the version of the output data differs from the output data.
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公开(公告)号：US20130275701A1
公开(公告)日：2013-10-17
申请号：US13777338
申请日：2013-02-26
Applicant: ARM LIMITED
Inventor： Dominic Hugo SYMES , Ola HUGOSSON , Donald FELTON , Sean Tristram ELLIS
IPC: G06F12/14
CPC classification number: G06F12/145
Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of descriptors defining the translations, wherein the page table base address is defined by the primary processor and cannot be amended by the secondary processor.
Abstract translation: 数据处理装置包括主处理器，被配置为执行安全数据处理操作和非安全数据处理操作的辅助处理器，以及被配置为在执行安全数据处理操作时存储由辅助处理器使用的安全数据的存储器，并且被配置为存储 在执行非安全数据处理操作时由辅助处理器使用的非安全数据，其中所述安全数据不能被所述非安全数据处理操作访问，其中所述辅助处理器包括存储器管理单元，所述存储器管理单元被配置为管理对 来自二级处理器的存储器，所述存储器管理单元被配置为在所述辅助处理器使用的虚拟存储器地址和所述存储器使用的物理存储器地址之间执行转换，其中，所述转换根据页表基地址，所述页表基 地址识别存储位置 定义翻译的一组描述符的存储器，其中页表基地址由主处理器定义并且不能被辅助处理器修改。
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Patent Agency Ranking
公开(公告)号：US20240248621A1
公开(公告)日：2024-07-25
申请号：US18099627
申请日：2023-01-20
Applicant: Arm Limited
CPC classification number: G06F3/0626 , G06F3/0644 , G06F3/0673 , G06F7/52
Abstract: A processor to generate accumulated data comprising, for an operation cycle: performing an operation on a first bit range of a set of first input data to generate a set of operation data, which is accumulated with stored data within a first storage device. A lowest n bits of the accumulated data are accumulated with first further stored data within a first bit range of a second storage device, and are bit-shifted from the first storage device. Further accumulated data is generated, comprising, for an operation cycle: performing the operation on a second bit range of the set of first input data to generate a further set of operation data, which is accumulated with the stored data within the first storage device. A lowest m bits of the further accumulated data is accumulated with second further stored data within a second bit range of the second storage device.
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公开(公告)号：US20220215613A1
公开(公告)日：2022-07-07
申请号：US17647137
申请日：2022-01-05
Applicant: Arm Limited
Inventor： Edvard FIELDING , Dominic Hugo SYMES
Abstract: When performing anisotropic filtering when sampling a texture to provide an output sampled texture value for use when rendering an output in a graphics processing system, a number of positions for which to sample the texture along an anisotropy direction along which samples will be taken in the texture is determined by determining the square root of the coefficient F for an ellipse having the form Ax2+Bxy+Cy2=F corresponding to the projection of the sampling point for which the texture is being sampled onto the surface to which the texture is to be applied, and using the determined square root of the ellipse coefficient F to determine the number of positions for which samples should be taken along the anisotropy direction in the texture.
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公开(公告)号：US20210334643A1
公开(公告)日：2021-10-28
申请号：US16859062
申请日：2020-04-27
Applicant: Arm Limited
Abstract: A processing unit is described that receives an instruction to perform a first operation on a first layer of a neural network, block dependency data, and an instruction to perform a second operation on a second layer of the neural network. The processing unit performs the first operation, which includes dividing the first layer into a plurality of input blocks, and operating on the input blocks to generate a plurality of output blocks. The processing unit then performs the second operation after the first operation has generated a set number of output blocks defined by the block dependency data.
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公开(公告)号：US20210303307A1
公开(公告)日：2021-09-30
申请号：US16834833
申请日：2020-03-30
Applicant: Arm Limited
Inventor： Jens OLSON , John Wakefield BROTHERS, III , Jared Corey SMOLENS , Chi-wen CHENG , Daren CROXFORD , Sharjeel SAEED , Dominic Hugo SYMES
Abstract: Herein described is a method of operating an accumulation process in a data processing apparatus. The accumulation process comprises a plurality of accumulations which output a respective plurality of accumulated values, each based on a stored value and a computed value generated by a data processing operation. The method comprises storing a first accumulated value, the first accumulated value being one of said plurality of accumulated values, into a first storage device comprising a plurality of single-bit storage elements; determining that a predetermined trigger has been satisfied with respect to the accumulation process; and in response to the determining, storing at least a portion of a second accumulated value, the second accumulated value being one of said plurality of accumulated values, into a second storage device.
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公开(公告)号：US20250036363A1
公开(公告)日：2025-01-30
申请号：US18359655
申请日：2023-07-26
Applicant: Arm Limited
Inventor： Dominic Hugo SYMES
Abstract: Methods and apparatus for performing a flooring divide operation comprised of a plurality of multiply with right shift instructions. Wherein the multiply with right shift instructions comprises decoding the multiply with right shift instruction and obtaining a portion of signed input data. In response to the decoded instruction and receipt of signed input data portions, controlling processing circuitry to process the portion of the signed input data, selecting a multiplier based on a sign of the signed input data, such that when the sign is negative a first derived constant is selected, and when the sign is positive, a second derived constant is selected. Multiplied input data is then generated by multiplying the portion of the signed input data by the multiplier, and then shifting by the constant size. The shifted multiplied input data is then stored in a storage.
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