公开(公告)号：US10761976B2

公开(公告)日：2020-09-01

申请号：US15361804

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Mudit Bhargava ,  Joel Thornton Irby ,  Vikas Chandra

IPC: H04L9/08 ,  G06F12/02 ,  G11C13/00

Abstract: A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.

公开(公告)号：US10438022B2

公开(公告)日：2019-10-08

申请号：US15381222

申请日：2016-12-16

Applicant: ARM Limited

Inventor： Vikas Chandra ,  Mudit Bhargava

IPC: G06F21/00 ,  G06F21/72 ,  H04L9/00 ,  H04L9/06 ,  G06F21/75 ,  G06F21/76 ,  H03K19/177 ,  G09C1/06

Abstract: A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.

公开(公告)号：US10122384B2

公开(公告)日：2018-11-06

申请号：US15157814

申请日：2016-05-18

Applicant: ARM Limited

Inventor： Liangzhen Lai ,  Vikas Chandra ,  Gary Dale Carpenter

IPC: G11C29/00 ,  H03M13/29 ,  H03M13/27

Abstract: Various implementations described herein are directed to a memory device. The memory device includes a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device includes a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit interleaves data bits from multiple different data words and stores modified data words based on the multiple different data words.

公开(公告)号：US20170277817A1

公开(公告)日：2017-09-28

申请号：US15078824

申请日：2016-03-23

Applicant: ARM Limited

Inventor： Liangzhen Lai ,  Vikas Chandra

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A computer implemented system and method is provided for reducing failure in time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.

公开(公告)号：US09715965B2

公开(公告)日：2017-07-25

申请号：US14488647

申请日：2014-09-17

Applicant: ARM Limited

Inventor： Lucian Shifren ,  Vikas Chandra ,  Mudit Bhargava

IPC: H01C7/00 ,  H01G4/005 ,  H01C17/00 ,  H01C1/14 ,  H01G4/33 ,  H01C17/065 ,  G09C1/00 ,  H01G4/08 ,  H01G4/14 ,  H04L9/08

CPC classification number: H01G4/005 ,  G09C1/00 ,  H01C1/14 ,  H01C7/006 ,  H01C17/00 ,  H01C17/06586 ,  H01G4/08 ,  H01G4/14 ,  H01G4/33 ,  H04L9/0866 ,  H04L2209/12

Abstract: An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures 2 including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.

公开(公告)号：US20160253227A1

公开(公告)日：2016-09-01

申请号：US14633062

申请日：2015-02-26

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Mudit Bhargava ,  Paul Meyer ,  Vikas Chandra

IPC: G06F11/07 ,  G06F11/08 ,  G06F11/10

CPC classification number: G06F11/076 ,  G06F11/085 ,  G06F11/1012 ,  G06F11/1016

Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

Abstract translation: 本文描述的各种实现可以指代并且可以涉及用于与存储器一起使用的错误检测电路。 在一个实现中，集成电路可以包括具有多行存储器单元的存储器阵列，其中相应的行被配置为存储对应于数据字的数据字和一个或多个校验位。 集成电路还可以包括耦合到相应行并且被配置为基于检测存储在相应行中的数据字中的一个或多个位错误来生成一个或多个标志位值的在线错误检测电路。 集成电路还可以包括错误校正电路，其配置为响应于一个或多个生成的标志位值来校正存储在相应行中的数据字中的一个或多个位错误。