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    Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals
    11.
    发明申请
    Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals 有权
    用于产生具有来自多个输入时钟信号的可调相位关系的输出时钟信号的方法和装置

    公开(公告)号：US20060029172A1

    公开(公告)日：2006-02-09

    申请号：US11194494

    申请日：2005-08-01

    申请人： Claudio Andreotti ,  Edoardo Prete ,  Anthony Sanders

    发明人： Claudio Andreotti ,  Edoardo Prete ,  Anthony Sanders

    IPC分类号： H04L7/00

    CPC分类号： H03K5/13 ,  H03K2005/00286 ,  H04L7/0025

    摘要： Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s′, c′) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

    摘要翻译： 用于产生具有来自多个输入时钟信号的可调相位关系的输出时钟信号的方法和装置。 提供了一种用于产生输出时钟信号（o）的方法和装置，其中具有彼此具有预定相位关系的多个输入时钟信号（s，c）以相应的加权因子（A，1） -A），并且其中加上加权输入时钟信号（s'，c'），以便产生加法时钟信号（i）。 累加时钟信号（i）被积分在积分器（8）中并且可选地被放大以产生输出时钟信号（o）。 具有可调相位关系的输出时钟信号（o）可以通过这样一种方式产生，其中对输入时钟信号的要求不那么严格。

    Memory system and method for operating a memory system
    12.
    发明授权
    Memory system and method for operating a memory system 有权
    用于操作存储器系统的存储器系统和方法

    公开(公告)号：US07966469B2

    公开(公告)日：2011-06-21

    申请号：US11464215

    申请日：2006-08-14

    申请人： Maurizio Skerlj ,  Anthony Sanders

    发明人： Maurizio Skerlj ,  Anthony Sanders

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F13/1673

    摘要： A memory system, in particular a buffered memory system, e.g., a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. The memory system may include a first buffered memory module, and a second buffered memory module, wherein the first and the second buffered memory modules are adapted to be accessed in parallel. According to a further embodiment of the invention, a device is provided which is adapted to map consecutive accesses to the first or the second memory module to a parallel access of both the first and the second memory module.

    摘要翻译： 公开了一种存储器系统，特别是缓冲存储器系统，例如全缓冲存储器系统，用于操作存储器系统的方法以及与存储器系统一起使用的器件。 存储器系统可以包括第一缓冲存储器模块和第二缓冲存储器模块，其中第一和第二缓冲存储器模块适于并行访问。 根据本发明的另一实施例，提供了一种设备，其适于将对第一或第二存储器模块的连续访问映射到第一和第二存储器模块的并行访问。

    Memory system and method for operating a memory system
    14.
    发明申请
    Memory system and method for operating a memory system 有权
    用于操作存储器系统的存储器系统和方法

    公开(公告)号：US20090106504A1

    公开(公告)日：2009-04-23

    申请号：US11464215

    申请日：2006-08-14

    申请人： Maurizio Skerlj ,  Anthony Sanders

    发明人： Maurizio Skerlj ,  Anthony Sanders

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1673

    摘要： A memory system, in particular a buffered memory system, e.g., a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. The memory system may include a first buffered memory module, and a second buffered memory module, wherein the first and the second buffered memory modules are adapted to be accessed in parallel. According to a further embodiment of the invention, a device is provided which is adapted to map consecutive accesses to the first or the second memory module to a parallel access of both the first and the second memory module.

    摘要翻译： 公开了一种存储器系统，特别是缓冲存储器系统，例如全缓冲存储器系统，用于操作存储器系统的方法以及与存储器系统一起使用的器件。 存储器系统可以包括第一缓冲存储器模块和第二缓冲存储器模块，其中第一和第二缓冲存储器模块适于并行访问。 根据本发明的另一实施例，提供了一种设备，其适于将对第一或第二存储器模块的连续访问映射到第一和第二存储器模块的并行访问。

    Surgical guide for femoral resection
    16.
    发明授权
    Surgical guide for femoral resection 失效
    股骨切除手术指南

    公开(公告)号：US5578037A

    公开(公告)日：1996-11-26

    申请号：US338901

    申请日：1994-11-14

    申请人： Anthony Sanders ,  Ann M. Corbo

    发明人： Anthony Sanders ,  Ann M. Corbo

    IPC分类号： A61B17/15 ,  A61B17/56

    CPC分类号： A61B17/15

    摘要： A surgical resection guide enables a surgeon to resect a femoral neck, during a hip arthroplasty procedure, such that a femoral prosthesis can be implanted within a patient to preserve or closely approximate the anatomic center of rotation of the hip. The guide is able to be used for left or right hip arthroplasty procedures, with either anterior or posterior surgical approaches.

    摘要翻译： 手术切除指南使得外科医生能够在髋关节置换术期间切除股骨颈，使得股骨假体可植入患者体内以保持或紧密接近髋关节的解剖中心。 该指南能够用于左侧或右侧髋关节置换手术，无论是前路还是后路手术。

    LED LIGHTING DISTRIBUTION UNIT AND COMPONENTS THEREOF
    17.
    发明申请
    LED LIGHTING DISTRIBUTION UNIT AND COMPONENTS THEREOF 审中-公开
    LED照明分配单元及其组件

    公开(公告)号：US20160126686A1

    公开(公告)日：2016-05-05

    申请号：US14436506

    申请日：2013-10-18

    申请人： Anthony Sanders

    发明人： Anthony Sanders

    IPC分类号： H01R25/00 ,  H01R4/18 ,  H01R4/48

    CPC分类号： H01R25/00 ,  H01R4/18 ,  H01R4/4809 ,  H01R12/712 ,  H01R13/5833 ,  H01R13/642 ,  H01R13/68 ,  H01R25/003

    摘要： A distribution unit for distributing mains electricity to multiple LED lighting devices, said unit comprising a terminal box and one or more plugs, the terminal box being adapted for connection to mains electricity and to receive said plugs, and each plug being adapted for connection to individual LED lighting elements, wherein said terminal box comprises: a) a housing having an opening for a distribution wire carrying mains electricity; b) a circuit board having terminals for connection of live and neutral conductors of said wire; c) at least two conductive tracks on the surface of said circuit board each connecting to a respective one of said terminals; and d) a plurality of sockets in the housing each having a non-circular bore with a longitudinal bore axis, the bore intersecting the edge of the circuit board, wherein said tracks are not closer than 3 mm to the edge of the circuit board where a socket intersects the circuit board, and wherein each said plug comprises: a) a body having a cross-section corresponding with the bore of each socket whereby the body can be inserted into the socket in only one orientation of the body with respect to the socket about said bore axis; b) a lighting wire for connection to an LED lighting element extending from the body; and c) a plug element on the end of the body and including two spring terminals, one connected to each of a live and neutral conductor of the lighting wire, wherein the plug element engages with the edge of the circuit board when the plug is inserted in a socket by movement along said axis and, on further movement of the plug into the socket by more than the distance of said tracks to the edge of the circuit board, said spring terminals engage a respective one of said tracks to complete electrical connection with the mains electricity.

    摘要翻译： 一种用于将电力分配给多个LED照明装置的分配单元，所述单元包括接线盒和一个或多个插头，所述接线盒适于连接到电源并接收所述插头，并且每个插头适于连接到个体 LED照明元件，其中所述接线盒包括：a）具有用于承载主电源的配线的开口的壳体; b）具有用于连接所述线的带电和中性导体的端子的电路板; c）在所述电路板的表面上的至少两个导电轨道，每个连接到相应的一个所述端子; 以及d）所述壳体中的多个插座，每个具有具有纵向孔轴线的非圆形孔，所述孔与所述电路板的边缘相交，其中所述轨道距离所述电路板的边缘不超过3mm 插座与电路板相交，并且其中每个所述插头包括：a）具有对应于每个插座的孔的横截面的本体，其中主体可以相对于主体的一个取向方向插入插座中 围绕所述孔轴线插入; b）用于连接到从身体延伸的LED照明元件的照明线; 以及c）所述主体端部上的插头元件，并且包括两个弹簧端子，一个连接到所述照明线的带电和中性导体中的每一个，其中当所述插头插入时，所述插头元件与所述电路板的边缘接合 在插座中沿着所述轴线移动，并且在将插头进一步移动到插座中超过所述轨道到电路板的边缘的距离之后，所述弹簧端子接合相应的一个所述轨道，以完成与 电源。

    Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage
    19.
    发明授权
    Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage 有权
    用于连接需要第一电源电压的第一电路和需要第二电源电压的第二电源电路的概念

    公开(公告)号：US07405591B2

    公开(公告)日：2008-07-29

    申请号：US11641545

    申请日：2006-12-19

    申请人： Georg Braun ,  Dirk Scheideler ,  Steve Wood ,  Richard Johannes Luyken ,  Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders

    发明人： Georg Braun ,  Dirk Scheideler ,  Steve Wood ,  Richard Johannes Luyken ,  Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017509

    摘要： An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

    摘要翻译： 使用第一电源电压的第一电路和使用不同于第一电源电压的第二电源电压的第二电路来连接设备。 该装置包括具有驱动器网络的驱动器电路，驱动器网络包括连接到可控开关的驱动器电源电压 可控开关包括电阻元件或与电阻元件分离。 接收器电路具有包括电阻元件和接收器电源电压端子的接收网络以及连接驱动电路和接收电路的连接线。 可控开关具有两个开关配置，第一开关配置导致连接线上的高电压，以及导致连接线上的低电压的第二开关配置。

    Memory buffer and method for buffering data
    20.
    发明申请
    Memory buffer and method for buffering data 审中-公开
    内存缓冲区和缓冲数据的方法

    公开(公告)号：US20080126624A1

    公开(公告)日：2008-05-29

    申请号：US11604665

    申请日：2006-11-27

    申请人： Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders ,  Gernot Steinlesberger ,  Maurizio Skerlj ,  Dirk Scheideler ,  Georg Braun ,  Steve Wood ,  Richard Johannes Luyken

    发明人： Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders ,  Gernot Steinlesberger ,  Maurizio Skerlj ,  Dirk Scheideler ,  Georg Braun ,  Steve Wood ,  Richard Johannes Luyken

    IPC分类号： G06F3/00

    CPC分类号： G11C7/1051 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/106

    摘要： A memory buffer comprises a first asynchronous latch chain interface connectable to at least one of a memory controller and a memory buffer, a second data interface connected to a memory device, and a circuit comprising a buffer and a processor, the circuit being coupled to the first and the second interfaces, so that data can be passed between the first interface and the buffer and between the second interface and the buffer and so that the processor is capable of processing at least one of the data from the first interface to the second interface and the data from the second interface according to a data processing functionality, wherein the data processing functionality of the processor is changeable by a programming signal received via an interface of a memory buffer.

    摘要翻译： 存储器缓冲器包括可连接到存储器控制器和存储器缓冲器中的至少一个的第一异步锁存链接口，连接到存储器件的第二数据接口以及包括缓冲器和处理器的电路，该电路耦合到 第一和第二接口，使得数据可以在第一接口和缓冲器之间以及第二接口和缓冲器之间传递，使得处理器能够处理从第一接口到第二接口的数据中的至少一个 以及根据数据处理功能的来自第二接口的数据，其中处理器的数据处理功能可以通过经由存储器缓冲器的接口接收的编程信号来改变。