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    CONCEPT FOR INTERFACING A FIRST CIRCUIT REQUIRING A FIRST SUPPLY VOLTAGE AND A SECOND SUPPLY CIRCUIT REQUIRING A SECOND SUPPLY VOLTAGE
    1.
    发明申请
    CONCEPT FOR INTERFACING A FIRST CIRCUIT REQUIRING A FIRST SUPPLY VOLTAGE AND A SECOND SUPPLY CIRCUIT REQUIRING A SECOND SUPPLY VOLTAGE 有权
    用于接收需要第一电源电压的第一电路和需要第二电源电压的第二电源电路的概念

    公开(公告)号：US20080143386A1

    公开(公告)日：2008-06-19

    申请号：US11641545

    申请日：2006-12-19

    申请人： Georg Braun ,  Dirk Scheideler ,  Steve Wood ,  Richard Johannes Luyken ,  Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders

    发明人： Georg Braun ,  Dirk Scheideler ,  Steve Wood ,  Richard Johannes Luyken ,  Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017509

    摘要： An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

    摘要翻译： 使用第一电源电压的第一电路和使用不同于第一电源电压的第二电源电压的第二电路来连接设备。 该装置包括具有驱动器网络的驱动器电路，驱动器网络包括连接到可控开关的驱动器电源电压 可控开关包括电阻元件或与电阻元件分离。 接收器电路具有包括电阻元件和接收器电源电压端子的接收网络以及连接驱动电路和接收电路的连接线。 可控开关具有两个开关配置，第一开关配置导致连接线上的高电压，以及导致连接线上的低电压的第二开关配置。

    Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage
    6.
    发明授权
    Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltage 有权
    用于连接需要第一电源电压的第一电路和需要第二电源电压的第二电源电路的概念

    公开(公告)号：US07405591B2

    公开(公告)日：2008-07-29

    申请号：US11641545

    申请日：2006-12-19

    申请人： Georg Braun ,  Dirk Scheideler ,  Steve Wood ,  Richard Johannes Luyken ,  Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders

    发明人： Georg Braun ,  Dirk Scheideler ,  Steve Wood ,  Richard Johannes Luyken ,  Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017509

    摘要： An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

    摘要翻译： 使用第一电源电压的第一电路和使用不同于第一电源电压的第二电源电压的第二电路来连接设备。 该装置包括具有驱动器网络的驱动器电路，驱动器网络包括连接到可控开关的驱动器电源电压 可控开关包括电阻元件或与电阻元件分离。 接收器电路具有包括电阻元件和接收器电源电压端子的接收网络以及连接驱动电路和接收电路的连接线。 可控开关具有两个开关配置，第一开关配置导致连接线上的高电压，以及导致连接线上的低电压的第二开关配置。

    Memory buffer and method for buffering data
    7.
    发明申请
    Memory buffer and method for buffering data 审中-公开
    内存缓冲区和缓冲数据的方法

    公开(公告)号：US20080126624A1

    公开(公告)日：2008-05-29

    申请号：US11604665

    申请日：2006-11-27

    申请人： Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders ,  Gernot Steinlesberger ,  Maurizio Skerlj ,  Dirk Scheideler ,  Georg Braun ,  Steve Wood ,  Richard Johannes Luyken

    发明人： Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders ,  Gernot Steinlesberger ,  Maurizio Skerlj ,  Dirk Scheideler ,  Georg Braun ,  Steve Wood ,  Richard Johannes Luyken

    IPC分类号： G06F3/00

    CPC分类号： G11C7/1051 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/106

    摘要： A memory buffer comprises a first asynchronous latch chain interface connectable to at least one of a memory controller and a memory buffer, a second data interface connected to a memory device, and a circuit comprising a buffer and a processor, the circuit being coupled to the first and the second interfaces, so that data can be passed between the first interface and the buffer and between the second interface and the buffer and so that the processor is capable of processing at least one of the data from the first interface to the second interface and the data from the second interface according to a data processing functionality, wherein the data processing functionality of the processor is changeable by a programming signal received via an interface of a memory buffer.

    摘要翻译： 存储器缓冲器包括可连接到存储器控制器和存储器缓冲器中的至少一个的第一异步锁存链接口，连接到存储器件的第二数据接口以及包括缓冲器和处理器的电路，该电路耦合到 第一和第二接口，使得数据可以在第一接口和缓冲器之间以及第二接口和缓冲器之间传递，使得处理器能够处理从第一接口到第二接口的数据中的至少一个 以及根据数据处理功能的来自第二接口的数据，其中处理器的数据处理功能可以通过经由存储器缓冲器的接口接收的编程信号来改变。

    Clock and data recovery circuit including first and second stages
    10.
    发明申请
    Clock and data recovery circuit including first and second stages 审中-公开
    时钟和数据恢复电路包括第一和第二阶段

    公开(公告)号：US20070183552A1

    公开(公告)日：2007-08-09

    申请号：US11346903

    申请日：2006-02-03

    申请人： Anthony Sanders ,  Dirk Scheideler ,  Edoardo Prete

    发明人： Anthony Sanders ,  Dirk Scheideler ,  Edoardo Prete

    IPC分类号： H03D3/24

    CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0995

    摘要： A clock and data recovery circuit including a first circuit and a second circuit. The first circuit is configured to receive a clock signal and a phase control signal and to lock onto the clock signal and provide a cleaned clock signal. The second circuit is configured to receive a data signal and the cleaned clock signal and to sample the data signal via the cleaned clock signal and provide the phase control signal. The first circuit adjusts the phase of the cleaned clock signal based on the phase control signal.

    摘要翻译： 一种包括第一电路和第二电路的时钟和数据恢复电路。 第一电路被配置为接收时钟信号和相位控制信号，并锁定到时钟信号上并提供清洁的时钟信号。 第二电路被配置为接收数据信号和清除的时钟信号，并且经由清除的时钟信号对数据信号进行采样并提供相位控制信号。 第一个电路基于相位控制信号来调整清除的时钟信号的相位。